Synchronous semiconductor device output circuit with reduced dat

Details Synchronous semiconductor device output circuit with reduced dat Synchronous semiconductor device output circuit with reduced dat

1999-03-09

2000-04-04

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518907, G11C 1604

Patent

active

060469439

ABSTRACT:
A data output system (100) is disclosed. The data output system (100) includes a number of data output paths (102a-102h) which provide data output signals (DQ0-DQ7) to a data bus. An invert data path 104 provides an invert data signal (INVOUT) that indicates when the data output signals (DQ0-DQ7) have been inverted to reduce the number of transitions on the data bus. A voter circuit (106) determines when data output signal inversion occurs, and includes a local data comparator (132a-132h) associated with each data output path (102a-102h). Each data comparator (132a-132h) compares a current data output signal (D0-D7) with a next data output signal (DN0-DN7), and in response thereto, generates a differential on a pair of data compare lines (138 and 140). The differential on the data compare lines (138 and 140) is amplified by a differential amplifier (136) to generate the invert output signal (INVN) for the following data output cycle.

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Nakamura et al., "A 500-MHz 4-Mb CMOS Pipeline-Burst Cache SRAM with Point-to-Point Noise Reduction Coding I/O", IEEE Journal of Solid-State Circuits, pp. 1758-1765, Nov. 1997.
Stan et al., "Bus-Invert Coding for Low-Power I/O", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 49-58, vol. 3, No. 1, Mar. 1995.

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