Synchronous pipeline with normally transparent pipeline stages

Details Synchronous pipeline with normally transparent pipeline stages Synchronous pipeline with normally transparent pipeline stages

2006-07-11

2006-07-11

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C712S219000, C713S323000

Reexamination Certificate

active

07076682

ABSTRACT:
A synchronous pipeline segment and an integrated circuit (IC) including the segment. The segment includes an input stage, an output stage and at least one intermediate stage. A place holder latch associated with each stage indicates whether valid stage data is in the stage. A local clock buffer provides a local clock gating a corresponding stage. The input and output stages are normally opaque and intermediate stages are normally transparent. Data items pass locally asynchronously between the input and output stages and are separated by opaque gated intermediate stages.

REFERENCES:
patent: 6393579 (2002-05-01), Piazza
patent: 6609209 (2003-08-01), Tiwari et al.
Hans Jacobson et al., “Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors”,Proceedings of the 11th International Symposium on High-Performance Computer Architecture (HPCA-Nov. 2005), Feb. 2005.
Hans M. Jacobson, “Improved Clock-Gating through Transparent Pipelining”, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (ISLPED'04), Aug. 2004.
Efthymiou et al., Adaptive Pipeline Depth Control for Processor Power Management, , Publisher: IEEE.
Shimada et al., Pipeline Stage Unification: A Low-Energy Consumption Technique for Future Mobile Processors, Aug. 23, 2003, pp. 326-329, Publisher: ACM, Published in: Seoul Korea.
Koppanalil et al., A Case for Dynamic Pipeline Scaling, Oct. 8, 2002, Publisher: ACM, Published in: Grenoble, France.

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