Synchronous memory having shared CRC and strobe pin

Details Synchronous memory having shared CRC and strobe pin Synchronous memory having shared CRC and strobe pin

2007-10-25

2009-12-22

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S200000, C365S233100, C365S193000

Reexamination Certificate

active

07636262

ABSTRACT:
A memory system having a memory element chip (DRAM) and a memory controller chips having a plurality of drivers and receivers and latches for transferred data. For writes clocks, write data and write for CRC (cyclic redundancy checks) is transferred to the DRAM from the memory controller and latched for error checking. The reads are clocked and the read data is received and transferred to a read data latch with also receives a clocked read strobe for verification of data integrity from DRAM. Each chip has a bi-functional pin that acts as a shared CRC pin during write and acts as a shared strobe pin during READ. Data transfers with the CRC signal and DQS signal are transferred across two paths CRC0/DQS and CRC1/DQS1. One could also transfer the CRC signal across one path with only the CRC0/DQS signal. Read operations have no CRC, and have no need for CRC because transfer errors during read can be detected by memory error correction coding (ECC). Write data provides source synchronous I/O data to said memory element chip needed for modem high speed memory communications.

REFERENCES:
patent: 6018778 (2000-01-01), Stolowitz
patent: 6067255 (2000-05-01), Jung et al.
patent: 6237052 (2001-05-01), Stolowitz
patent: 6549000 (2003-04-01), Ebiya
patent: 6715096 (2004-03-01), Kuge
patent: RE39421 (2006-12-01), Stolowitz
patent: 7200069 (2007-04-01), Jang et al.
patent: 2001/0014922 (2001-08-01), Kuge
“Processor fits into pin-limited design,” Integrated System Design, vol. 14, No. 153, p. 10-18.

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