Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reissue Patent
1998-12-02
2001-08-07
Powell, Mark R. (Department: 2122)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Reissue Patent
active
RE037316
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a synchronous LSI (large scale integrated circuit) device, and more specifically to a synchronous LSI memory device suitable for use with a high speed CPU.
BACKGROUND OF THE INVENTION
In general, in the case of a DRAM (Dynamic RAM) used as a main memory device of a computer, for instance, various control signals such as RAS (row access) signal, CAS (column access) signal, etc. are required. Conventionally, these control signals have been so far formed by processing a clock signal supplied as a signal for operating to the computer or CPU.
On the other hand, recently, the operating speed of the CPU has been improved to such an extent as to exceed that of the DRAM. Therefore, in a mini-computer or a work station composed of the CPU and the DRAM, the problem caused by the difference in operating speed between the two has been so far solved by use of the main memory constructed in the form of a plurality of banks (blocks) composed of DRAMs or in accordance with interleave operation of the memory. In this method of using the memory, however, the memory control procedure is complicated and thereby the cost of the memory increases inevitably.
On the other hand, another construction such that the memory is controlled internally in accordance with pipeline operation has been proposed. Where the memory is controlled in accordance with the simple pipeline operation, however, since the memory speed is determined by the data read speed from a core section, the pipeline method does not necessarily contribute to an improvement of the operating speed, so that a specific countermeasure must be taken for the memory control system to increase the memory speed to such an extent as to correspond to the CPU speed.
As described above, in the conventional synchronous LSI memory device, when the above-mentioned conventional memory operating methods such as interleave or bank switching, etc. are applied to a relatively small scale system such as a mini-computer or a work station, there exist problems in that the system cost is increased or down sizing is not attained. In addition, when the operating speed of the CPU is increased more and more as beyond 50 or 100 MHz, since the memory hierarchical structure must be constructed more ingeniously so as to use the CPU properly, with the result that the system is further complicated. For the reason as described above, there exists so far a strong need of memory structure and/or the memory control system which can match the operating speed of the CPU with that of the memory device.
SUMMARY OF THE INVENTION
With these problems in mind therefore, it is the object of the present invention to provide a synchronous LSI memory device which can correspond to a high speed CPU system, without complicating the system.
To achieve the above-mentioned object, the present invention provides a synchronous LSI memory device, comprising: memory cell array means (BK
1
, BK
2
) each having a plurality of memory cells; timing generating means (CLOCK MASKED SECT) for generating a first basic signal (CPOR) synchronous with a clock signal (CLK) and masked according to status of a control signal (CKE); signal generating means (SERIAL SYS CONTROL) for generating a second signal (CP) in synchronism with the first basic signal (CPOR) and stopping generating the second signal after a predetermined number of accesses OF in response to a stop signal (MRRST, MWSTP, LADA, BSTP); and control means (SHIFT REGISTER) for controlling said cell array means (BK
1
, BK
2
) on the basis of outputs of said timing signal generating means and said signal generating means.
Further, the present invention provides a synchronous LSI memory device, comprising: cell block means (CB) each having a plurality of memory cells; and data register means (WRITE REGISTER) for acquiring externally input data applied to first terminals (DQ) in synchronism with a clock signal (CLK), said data register means being provided with inputting registers (WRITE REGISTER) having a plurality of bits and connected to the respective first terminals; and when data are inputted, the inputting registers being controlled so that the respective plural bits are switched in sequence or not controlled so that the respective plural bits are set alternately to data input status.
Further, the present invention provides a synchronous LSI memory device, comprising: memory cell array means (BK
1
, BK
2
) each having a plurality of memory cells; timing generating means (TG) for generating a first basic signal (CPOR) synchronous with a clock signal (CLK) and masked according to status of a control signal (CKE); signal generating means (SERIAL SYS CONTROL) for generating a second signal (CP) in synchronism with the first basic signal (CPOR) and stopping generating the second signal (CP) after a predetermined number of accesses or in response to a stop signal (MRRST, MWSTP LADA, BSTP); control means for controlling said cell array means (BK
1
, BK
2
) on the basis of outputs of said timing signal generating means and said signal generating means (SERIAL SYS CONTROL); and mask control means (DQMR) for acquiring statuses of second terminals (DQM) in sequence into register means having the number of bits even-number times larger than that obtained during a cycle interval during which a column address is inputted, outputting the acquired data in sequence, inputting the outputted data, respectively to specific registers each having the number of bits even-number times larger than that obtained during the cycle interval during which the column address is inputted, and when data inputted through the second terminals (DQM) are in a first status, outputting signals for setting output circuits of the register means to a high impedance status in synchronism with the second signal (CP).
In the synchronous LSI memory device according to the present invention, when a plurality of the cell array means (each having a plurality of memory cells) for a plurality of banks are accessed, the timing generating means generates the basic signal, and the signal generating means generates the second signals on the basis of the basic signal. The cell array means are controlled by the control means on the basis of the second signals.
Further, when data are inputted to a plurality of the cell array means (each having a plurality of memory cells) for a plurality of banks, the data register means acquire externally inputted data through the input register means connected to the DQ terminals of the data register means in synchronism with the clock signal CLK. In this case, the register means are so controlled as to input the external inputted data in sequence and further a plurality of bits of the register means are set alternately to the data input enable status when the data input sequence is not changed.
Further, when a plurality of the cell array means (each having a plurality of memory cells) for a plurality of banks are accessed, the statuses of the DQM terminals of the register means having the number of bits half of that of a word length are acquired in sequence, and the acquired data are outputted in sequence. The outputted data are inputted to the registers whose number of bits is half of that of a specific word, respectively. Further, when the data inputted through the DQM terminals are in the first status, the impedance control means outputs a signal for setting the output circuits of the register means to a high impedance status, on the basis of the basic signal outputted by the timing generating means and in synchronism with the second signals outputted by the signal generating means.
Accordingly, in the synchronous LSI memory device according to the present invention, it is possible to operate the memory device whose access speed is lower than the CPU on the basis of a single high speed clock signal suitable for the CPU, so that the it is possible to simplify the clock control so as to be correspond to the higher speed CPU without complicating the system configuration.
REFERENCES:
patent: 5033001 (1991-07-01),
Chavis John
Foley & Lardner
Kabushiki Kaisha Toshiba
Powell Mark R.
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