Synchronous dynamic random access memory device

Details Synchronous dynamic random access memory device Synchronous dynamic random access memory device

2000-05-16

2001-04-10

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S194000, C365S189090, C365S226000

Reexamination Certificate

active

06215709

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to synchronously operated memory devices.
BACKGROUND OF THE INVENTION
Computer designers are always searching for faster memory devices that will allow them to design faster computers. A significant limitation on a computer's operating speed is the time required to transfer data between a processor and a memory circuit under a read or write data transfer. Memory circuits, such as dynamic random access memories (“DRAMs”), usually include a large number of memory cells arranged in one or more arrays, each having rows and columns. The memory cells provide locations at which the processor can store and retrieve data. The more quickly the processor can access the delta within the memory cells, the more quickly it can perform a calculation or execute a program using the data.
FIG. 1
shows, in part, a typical computer architecture. A central processing unit (“CPU”) or processor
50
is connected to a bus system
52
, which in turn is connected to a system or memory controller
54
. The processor
50
can also be connected, through the bus system
52
, to a datapath integrated circuit (“IC”)
56
. The memory controller
54
and the datapath IC
56
serve as interface circuitry between the processor
50
and a memory device
60
. Although the datapath IC
56
and the memory device
60
are shown as separate integrated datapath IC
56
and the memory device
60
are shown as separate integrated circuits, it will be understood that the circuitry of the datapath IC can be integrated into the memory device. The processor issues a command C and an address A which are received and translated by the memory controller
54
, which in turn applies command signals and an address to the memory device
60
. Corresponding to the processor-issued commands C and addresses A, data D is transferred between the processor
50
and the memory device
60
via the datapath IC
56
.
FIG. 2
illustrates a type of memory device
60
currently used, namely a synchronous dynamic random access memory (“SDRAM”), or its close relative, a synchronous graphics random access memory (“SGRAM”) circuit
100
. A main difference between the SDRAM and the SGRAM is the division of the memory therein. For example, the SGRAM has a double word width, i.e., it can access 32 bits in parallel for each address. The memory device
200
includes as its central memory element two memory array banks
101
A,
101
B, which operate under the control of a control logic circuit
102
. Each of the memory arrays
101
A, B includes a plurality of memory cells (not shown) arranged in rows and columns. For purposes of discussion, the memory device
200
has an 8-bit word width meaning that for each specified memory address (combined bank, row and column address) there is a one-to-one correspondence with 8 memory cells in one of the arrays
101
A, B. The processor
50
(see
FIG. 1
) also preferably operates on data elements of 8 bits each.
A system clock (not shown) provides a clock signal CLK to the control circuit
102
of the memory device
200
, as well as to the processor
50
and controller
54
(
FIG. 1
) accessing the memory device. However, the signal CLK must be precisely registered with other input signals, such as control signals described below, that are applied to the memory device
200
so that those input signals will be available to the memory device when the memory device
200
attempts to operate on those input signals. However, it is sometimes difficult to ensure that the CLK signal is precisely registered to the other input signals, particularly as clock frequencies increase at higher operating speeds. Moreover, the signal CLK may be corrupted by noise or transient signals that can adversely affect the operation of the memory device
200
, and, in some cases, the duration of the CLK signal may be too short for the proper operation of the memory device
200
. Precise registration of the CLK signal with other signals, as well as noise and other transients, are some of the problems that adversely affect the operation of conventional memory devices
60
and limit their operating speeds.
Command signals input to the control circuit
102
are decoded by command decode circuitry
104
. These signals are well known in the art, and include signals such as row address strobe ({overscore (RAS)}), column address strobe ({overscore (CAS)}) and write enable ({overscore (WE)}). (The line or bar over, or an “*” following, the acronym for a signal generally indicates that the active state for the particular signal is a logical low value.)
Distinct combinations of the various command signals constitute distinct commands. For example, the combination of {overscore (RAS)} low, {overscore (CAS)} high and {overscore (WE)} low can represent a PRECHARGE command. Examples of other well known commands include ACTIVE, READ, WRITE and NOP. Responding to the applied command, the control circuit
102
sends control signals on control lines
103
A-H to other parts of the memory device
200
, controlling the timing and access to the memory cells in arrays
101
A,
101
B.
In operation, an address is input to an address register
106
, indicating the memory location to be accessed. The address specifies one of the memory banks
10
A, B and a row and column address within the specified bank. The address register
106
provides the address information to the control circuit
102
, and to a row-address multiplexer
107
and a column-address latch and decode circuit
110
. The row-address multiplexer
107
multiplexes the row address information and provides it to one row-address latch and decode circuit
108
A or
108
B corresponding to the one of the memory banks
101
A, B to be accessed, respectively. Each of the row latch and decode circuits
108
A,
108
B takes a row address provided by the row-address multiplexer
107
and activates a selected row of memory cells (not shown) in the memory array
101
A,
101
B by selecting one of several row access lines
112
A,
112
B, all respectively. The column latch and decode circuit
110
takes a column address provided by the address register
106
and selects one of several column access lines
114
A,
114
B, each of which is coupled to one of the memory arrays
101
A,
101
B by an I/O interface circuit
116
A,
116
B, all respectively. Each of the I/O interface circuits
116
A,
116
B selects the memory cell(s) corresponding to the column location in an activated row. The I/O interface circuits
116
include sense amplifiers which determine and amplify the logic state of the selected memory cells, and I/O gating of data to and from a data I/O register
118
. The data register
118
is connected to a data bus which is used to input and output data to and from the memory device
200
over DQ lines.
Data transfer cycles typically involve several steps and each step) takes time. For example, a read access requires the control circuit
102
of the memory device
200
to decode certain commands and a memory address. The control circuit
102
must then provide control signals to the circuitry accessing the memory array banks
101
A,
101
B in order to activate the selected row in the selected memory bank, allow time for sense amplifiers to develop signals from the selected column in the memory bank, transfer data from these sense amplifiers to the data register
118
where the data is then made available on the data bus, and terminate the cycle by precharging the row for subsequent access. Steps that are particularly time consuming include the activation step and the precharge step which can result in a substantial read latency (the time between registration in the memory device of a read command and the availability of the accessed data on the data bus).
Other steps during data transfer cycles also require significant amounts of time. For example, a memory device having a sequential or “burst” mode for generating serial addresses requires a finite amount of time for initiating the burst mode, and thereafter sequentially generating the subsequent addresses. U.S. Pat

Affiliated with

Also associated with

Rating

Synchronous dynamic random access memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous dynamic random access memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous dynamic random access memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2555514