Synchronous DRAM with alternated data line sensing

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

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365208, 365190, G11C 700

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active

058124730

ABSTRACT:
A synchronous dynamic random access memory (SDRAM) has a plurality of memory cell arrays including a plurality of bit line pairs with each bit line connected to a plurality of memory cells, a plurality of sense amplifiers with each sense amplifier connected to a bit line pair of each memory cell array through a bank select switch, and a plurality of data line pairs. A plurality of pass gates includes a first pair of pass gates connecting a sense amplifier output of a bit line pair to a first data line pair, and a second pair of pass gates connecting the sense amplifier output of a bit line pair to a second data line pair, whereby each bit line pair is connectable through a sense amplifier to first and second data line pairs. In operation, the first data line pair and the second data line pair are toggled alternately in connection to the bit line pairs by alternating column select line signals (CSLA, CSLB).

REFERENCES:
patent: 5367492 (1994-11-01), Kawamoto
patent: 5544125 (1996-08-01), Yokoyama
patent: 5594704 (1997-01-01), Konishi
Yunho Choi et al., "16-Mb Synchronous DRAM with 125-Mbyte/s Data Rate", IEEE Journal of Solid-State Circuits, 29(4) 529-531 (Apr. 1994).
Natsuki Kushiyama et al., "A 500-Megabyte/s Data-Rate 4.5M DRAM", IEEE Journal of Solid-State Circuits, 28(4) 490-491 (Apr. 1993).
Toshio Sunga et al., "A Full Bit Prefetch Architecture for Synchronous DRAM's", IEEE Journal of Solid-State Circuits 30(9) 998-999 (Sep. 1995).
Toshio Sunaga, "A Full Bit Prefetch DRAM Sensing Circuits", IEEE Journal of Solid-State Circuits, 31(6) 767-768 (Jun. 1996).
Yasuhiro Takai et al., "250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Archnitecture", IEEE Journal of Solid-State Circuits, 29(4) 426-427 (Apr. 19, 1994).

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