Synchronous dram having a plurality of latency modes

Details Synchronous dram having a plurality of latency modes Synchronous dram having a plurality of latency modes

1997-03-17

1998-11-10

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711169, 395879, 395552, 365199, 365233, G06F 1316

Patent

active

058359567

ABSTRACT:
A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

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