Synchronous data sampling circuit

Details Synchronous data sampling circuit Synchronous data sampling circuit

2000-06-02

2001-06-26

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S144000, C326S094000

Reexamination Certificate

active

06252441

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 99-23489, filed on Jun. 22, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a data sampling circuit.
Synchronous DRAMs, which operates in synchronization with a system clock signal, have been developed for the high speed operation of semiconductor memory devices. Also, dual data rate (DDR) synchronous DRAMs and Rambus DRAMs, to which data is input and from which data is output in synchronization with the rising and falling edges of a clock signal, have recently been developed to satisfy demands for higher operation frequency.
FIG. 1
is a circuit diagram of a data sampling circuit using a conventional DDR method.
FIG. 2
is a timing diagram of the data sampling circuit using the DDR method, shown in FIG.
1
.
Referring to
FIGS. 1 and 2
, in the data sampling circuit of the conventional DDR method, a flip-flop
11
samples data Data
1
input through an input and output pad D
Q
and outputs the sampled data to a data input and output line D
IO
at the falling edge of a clock signal CLOCK, i.e., where the level of the clock signal CLOCK is transited from a logic “high” level to a logic “low” level. Also, a flip-flop
13
samples data Data
2
input through the input and output pad D
Q
and outputs the sampled data to the data input and output line D
IO
at the rising edge of the clock signal CLOCK, i.e., where the level of the clock signal CLOCK transits from the logic “low” level to the logic “high” level.
Therefore, according to the data sampling scheme of the conventional DDR method, it is possible to sample only two data items during one cycle (t
CYCLE
) of the clock signal (CLOCK).
SUMMARY OF THE INVENTION
To solve the above problem, it is an object of the present invention to provide a synchronous data sampling circuit by which it is possible to sample four data items during one cycle of a clock signal in order to increase data sampling efficiency.
It is another object of the present invention to provide a synchronous data sampling method by which it is possible to sample four data items during one cycle of a clock signal in order to increase data sampling efficiency.
Accordingly, to achieve the first object, there is provided a synchronous data sampling circuit comprising first and second pulse signal generators and first through fourth sampling means.
The first pulse signal generator receives a clock signal and generates a first pulse signal during a logic “low” interval of the clock signal. The second pulse signal generator receives the clock signal and generates a second pulse signal during a logic “high” interval of the clock signal.
The first sampling unit samples first data input through the input port and outputs the sampled first data to the output port in response to the falling edge of the clock signal. The second sampling unit samples second data input through the input port and outputs the sampled second data to the output port in response to an edge of the first pulse signal. The third sampling unit samples third data input through the input port and outputs the sampled third data to the output port in response to the rising edge of the clock signal. The fourth sampling unit samples fourth data input through the input port and outputs the sampled fourth data to the output port, in response to the edge of the second pulse signal.
Preferably, the input nodes of the first through fourth sampling means are commonly connected to an input port to which data items are input and the output nodes of the first through fourth sampling means are commonly connected to an output port.
The edge of the first pulse signal may be either a rising edge or a falling edge. Similarly, the edge of the second pulse signal may be either a rising edge or a falling edge.
The first pulse signal generator may comprise a non-inverting delay for delaying the clock signal; a inverting delay for inverting and delaying the clock signal, the inverting delay having a second delay time that is shorter than a first delay time of the non-inverting delay; and an AND gate for performing an AND operation on the output signal of the non-inverting delay and the output signal of the inverting delay and outputting a result of the AND operation as the first pulse signal.
The second pulse signal generator may comprise a non-inverting delay for delaying the clock signal; an inverting delay for inverting and delaying the clock signal, the inverting delay having a second delay time that is shorter than a first delay time of the non-inverting delay; and an OR gate for performing an OR operation on the output signal of the non-inverting delay and the output signal of the inverting delay and outputting a result of the OR operation as the second pulse signal.
The first through fourth sampling means preferably comprise first through fourth flip-flops.
The first pulse generator may comprise a non-inverting delay for delaying the clock signal; an inverting delay for inverting and delaying the clock signal, the inverting delay having a second delay time that is shorter than a first delay time of the non-inverting delay; and a NAND gate for performing a NAND operation on the output signal of the non-inverting delay and the output signal of the inverting delay, and outputting a result of the NAND operation as the first pulse signal.
The second pulse signal generator may comprise a non-inverting delay for delaying the clock signal; an inverting delay for inverting and delaying the clock signal, the inverting delay having a second delay time that is shorter than a first delay time of the non-inverting delay; and a NOR gate for performing a NOR operation on the output signal of the non-inverting delay and the output signal of the inverting delay, and outputting a result of the NOR operation as the second pulse signal.
To achieve the second object, there is provided a synchronous data sampling method, comprising receiving a clock signal and generating a first pulse signal during a logic “low” interval of the clock signal; receiving the clock signal and generating a second pulse signal during a logic “high” interval of the clock signal; sampling first data input through the input port and outputting the sampled first data to the output port, in response to the falling edge of the clock signal; sampling second data input through the input port and outputting the sampled second data to the output port, in response to an edge of the first pulse signal; sampling third data input through the input port and outputting the sampled third data to the output port, in response to the rising edge of the clock signal; and sampling fourth data input through the input port and outputting the sampled fourth data to the output port, in response to an edge of the second pulse signal.
The edge of the first pulse signal may be either a rising edge or a falling edge. Similarly, the edge of the second pulse signal may be either a rising edge or a falling edge.
The generating of the first pulse signal may comprise delaying the clock signal for a first time period to produce a first signal; inverting the clock signal and delaying the inverted clock signal for a second time period shorter than the first time period, to produce a second signal; and performing an AND operation on the first and second signals to generate the first pulse signal.
The generating of the second pulse signal may comprise delaying the clock signal for a first time period to produce a first signal; inverting the clock signal and delaying the inverted clock signal for a second time period shorter than the first time period, to produce a second signal; and performing an OR operation on a the first and second signals to generate the second pulse signal.
The generating of the first pulse signal may comprise delaying the clock signal for a first time period to produce a first signal; inverting the clock signal and delaying the invert

Affiliated with

Also associated with

Rating

Synchronous data sampling circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous data sampling circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous data sampling circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2455849