Synchronous clock multiplexing and output-enable

Details Synchronous clock multiplexing and output-enable Synchronous clock multiplexing and output-enable

2010-10-22

2011-11-08

Ismail, Shawki S (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Reexamination Certificate

active

08054103

ABSTRACT:
A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided as inputs to the pair of logic gates, which generate respective logic outputs. The output block contains synchronizers clocked by respective input signals, and receives the logic outputs also as inputs. The output block provides a selected one of the input signals as an output, the provision of the selected input signal being accomplished in a synchronous fashion. Enabling and disabling of the output are also performed synchronously.

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