Synchronous burst-access memory

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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365236, 365233, G11C 700

Patent

active

052688658

ABSTRACT:
A synchronous burst-access memory latches a row address strobe signal, a column address strobe signal, and address signals in synchronization with a clock signal. Data are stored in rows and columns in a memory cell array. Data in a selected row are input and output in serial bursts in synchronization with the clock signal, starting from a selected column. The row and initial column address are provided as external inputs; subsequent column addresses are generated by an internal address counting circuit. A word-line driving circuit for a synchronous memory uses transparent latches to latch the row address strobe signal and address signals, enabling row address decoding to be completed prior to synchronization with the clock signal.

REFERENCES:
patent: 4513372 (1985-04-01), Ziegler et al.
patent: 4608678 (1986-08-01), Threewitt
patent: 4829484 (1989-05-01), Arimoto
patent: 4891791 (1990-01-01), Iijima
patent: 4928265 (1990-05-01), Higuchi
patent: 4984217 (1991-01-01), Sato
patent: 5003510 (1991-03-01), Kamisaki
patent: 5016226 (1991-05-01), Hiwada
patent: 5111386 (1992-05-01), Fujishima
Electronic Design, vol. 36, No. 19, Aug. 25, 1988, Hasbruock Heights, New Jersey, pp. 93-96--Shakaib Iqbal "Internally Timed RAMs Build Fast Writable Control Stores", p. 95, line 15-p. 96, line 16, FIG. 4.

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