Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1995-12-04
1998-02-03
Zarabian, A.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365236, 365233, G11C 700
Patent
active
RE0357235
ABSTRACT:
A synchronous burst-access memory latches a row address strobe signal, a column address strobe signal, and address signals in synchronization with a clock signal. Data are stored in rows and columns in a memory cell array. Data in a selected row are input and output in serial bursts in synchronization with the clock signal, starting from a selected column. The row and initial column address are provided as external inputs; subsequent column addresses are generated by an internal address counting circuit. A word-line driving circuit for a synchronous memory uses transparent latches to latch the row address strobe signal and address signals, enabling row address decoding to be completed prior to synchronization with the clock signal.
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Electronic Design, vol. 36, No. 19, Aug. 25, 1988, pp. 93-96--Shakaib Iqbal, "Internally Timed RAMs Build Fast Writable Control Stores".
OKI Electric Industry Co., Ltd.
Zarabian A.
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