Synchronizing logic avoiding metastability

Details Synchronizing logic avoiding metastability Synchronizing logic avoiding metastability

1996-08-08

1998-08-11

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Metastable state prevention

326 93, 327145, 327198, H03L 700

Patent

active

057932271

ABSTRACT:
An apparatus and method for controlling and rectifying possible metastability situations having a first circuit with a first clock signal (CLOCK1) at a first clock rate and a second circuit with a second clock signal (CLOCK2) at a second clock rate, the second circuit having an input circuit coupled to the first circuit and receiving signals therefrom. A control circuit for controlling possible metastability situations arising in communication between the first circuit and the second circuit is also provided. The control circuit receives as input the first clock signal and the second clock signal and provides a shifting of at least one of the two clock signals, in such a way that a possible metastable state of the input circuit is avoided.

REFERENCES:
patent: 4949361 (1990-08-01), Jackson
patent: 5008904 (1991-04-01), Mangelsdorf et al.
patent: 5034967 (1991-07-01), Cox et al.
patent: 5099477 (1992-03-01), Taniguchi et al.
patent: 5256912 (1993-10-01), Rios
patent: 5548620 (1996-08-01), Rogers

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