Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2001-01-25
2004-10-26
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C345S522000
Reexamination Certificate
active
06810483
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method and system for improving clock speed for data and function opcodes between a first device at a first clock speed and a second device at a second clock speed.
As computational capabilities continue to increase, more powerful applications are continually being developed. These new applications have been used in a variety of areas, such as in audio/video (AV) applications. Reusable Internet protocol (IP) cores, such as AV cores, typically use a great deal of computationally intensive logic and run at high clock speeds. These AV cores generally use a first clock for an application layer and a second clock for internal logic. The internal logic is typically implemented using a standard protocol, such as IEEE-1394. The application layer requires a faster clock speed than the internal logic.
Currently, computations are performed at the first clock speed in the application layer and the results are sent to a synchronizing element. The results are then used in the internal logic at the slower, second clock speed. The synchronizing element has typically been implemented by a first in first out (FIFO) type device. Doing computations in the faster, first clock domain requires tight synthesis and imposes numerous layout constraints on the compute logic. These problems are generally resolved by slowing the first clock speed to accommodate the computations. Unfortunately, this reduces the performance of the application layer.
Accordingly, there is a need for a method and system for providing data and function opcodes between a first device, such as an application layer, at a first clock speed and a second device, such as internal logic, at a second clock speed. Such a method and system should reduce, or lessen, requirements of synthesis and logic layout and which reduces a need to slow the first clock speed in order to perform complex computations.
SUMMARY OF THE INVENTION
This need is met by a method and system in accordance with the present invention in which synchronized data and function opcodes are passed from an application layer having a first clock speed to a logic circuit having a slower second clock speed relative to the first clock speed. Computations on the data based on an associated function opcodes are then performed by compute logic in the logic circuit running at the second clock speed. Preferably, the second clock speed is slower than the first clock speed. For example, the second clock speed may be approximately 50 MHz and the first clock speed approximately 100 MHz.
In accordance with the present invention, a method is provided for synchronizing data between an application -having a first clock speed and a circuit, such as a logic circuit, having a second clock speed slower than the first clock speed. Data and a function opcode are received from the application. The data and the function opcode are then provided to the circuit in accordance with the second clock speed. A computation on at least a portion of the data based on the function opcode is performed at the second clock speed. The computation may be performed by compute logic in the circuit.
The second clock speed may be determined by a standard, such as an IEEE-1394 high speed serial bus standard. The IEEE-1394 standard sets the second clock speed at approximately 50 MHz. The data may be received from the application and provided to the circuit by a first in first out type device which may be implemented as a soft macro.
In accordance with another aspect of the present invention, a method for synchronizing data sent from an application layer having a first clock speed to a logic circuit having a second clock speed is provided. The second clock speed is dictated, or is in accordance with, a standard, such as IEEE-1394. The method comprises the steps of: defining a set of computations to be performed at the second clock speed; receiving data from the application layer for which one of the set of computations is to be performed; receiving a function opcode representative of the one of the set of computations; sending the data and the function opcode to the logic circuit; and performing the one of the set of computations on the data at the second clock speed.
In accordance with yet another aspect of the present invention, a system for transmitting data between an application layer having a first clock speed and a logic circuit having a second clock speed. A synchronizing element receives the data and a function opcode from the application layer and transmits the data and function opcode in accordance with the second clock speed. A compute logic opening at the second clock speed receives the data and the function operand and performs a computation associated with the function opcode on the data.
These and other features and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings and the appended claims.
REFERENCES:
patent: 5917505 (1999-06-01), Larson
patent: 6061073 (2000-05-01), Larson
Bever Hoffman & Harms LLP
Harms Jeanette S.
Lee Thomas
Synopsys Inc.
Wang Albert
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