Synchronizing and aligning differing clock domains

Details Synchronizing and aligning differing clock domains Synchronizing and aligning differing clock domains

2005-11-08

2005-11-08

Cottingham, John R. (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Reexamination Certificate

active

06963991

ABSTRACT:
Embodiments of the invention relate to a memory control hub (MCH) clock master of an MCH. Typically, in a computer system, a processor is coupled to the MCH by a front-side bus (FSB). Further, an input/output control hub (ICH) is typically coupled to the MCH by a back-side bus or Hub Link. In one embodiment, a host phase locked loop (HPLL) of the MCH clock master receives an FSB clock signal transmitted on the FSB and generates a local synchronous clock signal based upon the FSB clock signal. A delayed lock loop (DLL) of the MCH clock master also receives the FSB clock signal and generates a system clock signal. Particularly, the DLL synchronizes the system clock signal to the local synchronous clock and drives the system clock signal to many different devices on the board.

REFERENCES:
patent: 6608528 (2003-08-01), Tam et al.
patent: 2002/0078273 (2002-06-01), Jacobs
patent: 2002/0112136 (2002-08-01), Fujii
INTEL, Intel 830 Chipset Platform Design Guide, Jan. 2002, Order No.:298339-003.

Affiliated with

Also associated with

Rating

Synchronizing and aligning differing clock domains does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronizing and aligning differing clock domains, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronizing and aligning differing clock domains will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3452899