Synchronizer circuit and method for reducing the occurrence of m

Details Synchronizer circuit and method for reducing the occurrence of m Synchronizer circuit and method for reducing the occurrence of m

1994-08-03

1996-04-23

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Metastable state prevention

326 97, 327145, 327207, H03K 1900, H03K 19082, H03K 190948

Patent

active

055107320

ABSTRACT:
A digital system including a synchronizer circuit which significantly reduces the occurrence of metastability conditions during data transfer between a first digital subsystem and a second digital subsystem is disclosed. The synchronizer circuit includes a master synchronizer cell and a slave synchronizer cell for handling data transfer from the first subsystem to the second subsystem. Each synchronizer cell includes a signal node, a discharge node, a first discharge patch and a second discharge path, both coupled between the signal node and the discharge node, and a control element coupled to the first discharge path and the second discharge path. The control element selectively activates the first discharge path and the second discharge path in response to an input signal.

REFERENCES:
patent: 4849658 (1989-07-01), Iwamura et al.
patent: 4914318 (1990-04-01), Allen
patent: 5121002 (1992-06-01), Matsuzawa et al.
patent: 5173626 (1992-12-01), Kudou et al.
patent: 5256912 (1993-10-01), Rios
patent: 5263173 (1993-11-01), Gleason
"The Design and Analysis of VLSI Circuits", by Dobberpuhl, Chapter 6, pp. 360-364, Addison Welsey, 1985.

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