Synchronized redundancy decoding systems and methods for integra

Details Synchronized redundancy decoding systems and methods for integra Synchronized redundancy decoding systems and methods for integra

1996-08-26

1998-07-07

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 3652257, G11C 700

Patent

active

057779317

ABSTRACT:
Redundancy decoding systems and methods for integrated circuit memory devices synchronize a redundancy decoding signal to allow the redundancy decoding signal to be output during an enabling period and to prevent output of the redundancy decoding signal otherwise. In particular, a redundancy decoder is synchronized to an output buffer so that the redundancy decoder generates a redundancy decoding signal during a time period which is independent of the identity of the programmed address. Accordingly, high speed selection of a redundancy word line is provided in synchronism with the conventional word line selection, so that address skew and improper operation of the redundancy system relative to the normal word line selection system is prevented.

REFERENCES:
patent: 5282165 (1994-01-01), Miyake
patent: 5457656 (1995-10-01), Fu
patent: 5544106 (1996-08-01), Koike

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