Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-14
2001-01-09
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S510000, C438S514000
Reexamination Certificate
active
06171914
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming both NLDD and N+ or PLDD and P+ regions in one implantation in the fabrication of integrated circuits.
(2) Description of the Prior Art
In scaling down semiconductor devices, thinner gate oxide and higher doped channels are required for short channel devices. These measures increase the electric field near the drain regions. Charge carriers are accelerated by the electric field and become “hot” carriers. These hot carriers can overcome the oxide barrier and inject into the gate or become trapped in the gate oxide degrading device performance. This is the so-called hot carrier effect and is discussed, for example, in
ULSI Technology
, by C. Y. Chang and S. M. Sze, McGraw-Hill Co, Inc, New York, N.Y., c. 1996, p. 480. The lightly doped drain (LDD) reduces this drain field, thereby alleviating the hot carrier effect. However, the conventional LDD process takes much cycle time and strenuous steps. The drain is conventionally formed by two implants.
U.S. Pat. No. 4,771,014 to Liou et al teaches a LDD CMOS process using unmasked blanket implants. U.S. Pat. No. 5,858,847 to Zhou et al forms the source/drain first using a photoresist block, and then implanting the LDD. U.S. Pat. No. 5,141,891 to Arima et al discloses a polysilicon source drain (PSD) and a LDD structure. U.S. Pat. No. 5,780,903 to Tsai et al forms an LDD using a photoresist ion implant mask and two implantations.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of source/drain and LDD implantation.
A further object of the invention is to provide a method of source/drain and LDD implantation using a single implantation step.
Yet another object is to provide a method of source/drain and LDD implantation wherein a single implantation through different resist thicknesses results in the simultaneous formation of both the source/drain and LDD regions.
In accordance with the objects of this invention, a method of source/drain and LDD implantation using a single implantation step is achieved. A gate electrode is formed in an active area on surface of a semiconductor substrate. The gate electrode and the semiconductor substrate are covered with a resist layer. The resist layer in the active area is exposed to lithography source, such as electron-beam direct writing, or other process, wherein a portion of the resist layer overlying the planned LDD regions is exposed to a first energy and a portion of the resist layer overlying the planned source/drain regions is exposed to a second energy greater than the first energy and wherein a portion of the resist layer outside of the active area is not exposed. The resist layer is developed to leave a resist mask having a first thickness in areas not exposed and to leave a resist mask having a second thickness in areas exposed to the first energy and to leave no resist mask in areas exposed to the second energy. Ions are implanted into the semiconductor substrate adjacent to the gate electrode wherein the ions implanted through no resist mask form the source/drain regions and wherein the ions implanted through the resist mask having the second thickness form the LDD regions to complete said simultaneous fabrication of the source/drain regions and LDD regions in the fabrication of an integrated circuit device.
REFERENCES:
patent: 4771014 (1988-09-01), Liou et al.
patent: 5141891 (1992-08-01), Arima et al.
patent: 5567629 (1996-10-01), Kubo
patent: 5780903 (1998-07-01), Tsai et al.
patent: 5858847 (1999-01-01), Zhou et al.
patent: 5882974 (1999-03-01), Gardner et al.
patent: 5888861 (1999-03-01), Chien et al.
Wolf, S., Tauber R.N.; Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, 1986, pp. 501-504.
Chang et al., “ULSI Technology,” The McGraw-Hill Co., Inc., New York, NY, c.1996, p. 480.
Liao Ni-Ko
Tzu San-De
Ackerman Stephen B.
Lattin Christopher
Niebling John F.
Pike Rosemary L. S.
Saile George O.
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