Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-04-03
2008-09-09
Lamarre, Guy J (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S731000, C714S733000, C714S734000
Reexamination Certificate
active
07424660
ABSTRACT:
A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An output signal from an output pin on the IC indicates the existence of a synchronization state to automated test equipment (ATE). After an ATE receives the output signal, it issues a resume signal through an IC input pin that causes the controllers to advance out of the synchronization state. The ATE controls the synchronization state length by delaying the resume signal. Synchronization states can be used in parametric test algorithms, such as for retention and IDDQ tests. Synchronization states can be incorporated into user-defined algorithms by software design tools that generate an HDL description of a BIST controller operable to apply the algorithm with the synchronization state.
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Cheng Wu-Tung
Hill Christopher John
Kebichi Omar
Mustafa Yahya M. Z.
Reuter Paul J.
Klarquist & Sparkman, LLP
Lamarre Guy J
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