Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2011-05-10
2011-05-10
Connolly, Mark (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S375000, C713S500000
Reexamination Certificate
active
07941684
ABSTRACT:
In one embodiment, an apparatus comprises one or more processors and a controller coupled to the processors. Each processor comprises at least one processor time stamp counter (TSC) and a first control unit configured to maintain the processor TSC. The controller comprises at least one controller TSC and a second control unit configured to maintain the controller TSC. The controller is configured to signal the processor responsive to determining that the processor TSC is out of synchronization with the controller TSC. In response to having been signalled that the processor TSC is out of synchronization, the processor is configured to resynchronize the processor TSC to the controller TSC before generating a result for a read TSC instruction. In response to having not been signalled that the processor TSC is out of synchronization, the processor is configured to generate the result responsive to the processor TSC without resynchronizing.
REFERENCES:
patent: 6480966 (2002-11-01), Rawson, III
patent: 7058838 (2006-06-01), Xu
patent: 2005/0058159 (2005-03-01), Chapman
U.S. Appl. No. 12/039,278, filed Feb. 28, 2008.
Kallal Robert M.
Serebrin Benjamin C.
Advanced Micro Devices , Inc.
Connolly Mark
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Yanchus, III Paul B
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