Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-05
2002-07-30
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S289000, C438S589000
Reexamination Certificate
active
06426260
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the cell structure and fabrication process of vertical power transistors. More particularly, this invention relates to switching speed improvement achieved by carrying out a high-energy body-conductivity-type-dopant implant, e.g., boron implant through the gate. The high-energy body-conductivity-type-dopant implant forms a reduced doping concentration zone, e.g., an n zone, under the gate that serves to reduce the gate-to-drain capacitance of a vertical DMOS planar device. Thus, the device switching speed is improved with the reduced gate-to-drain capacitance without significantly increasing the on-resistance.
2. Description of the Prior Art
Improvement of the switching speed of a low-voltage DMOS power device cannot be conveniently achieved for the reason that the epitaxial layer is formed to have a low resistivity. A low resitivity is of course a desirable design feature for the low voltage device as a typical prior art device
10
shown in FIG.
1
. However, an epitaxial layer
15
with a low resistivity as shown often causes a high capacitance between the gate
20
and the drain
15
. As will be further described below, the switching speed of the DMOS device
10
is adversely affected by a high gate-to-drain capacitance.
FIG. 1B
is an equivalent circuit diagram of the parasitic capacitors between the gate
20
and the drain
15
. There is a first parasitic capacitor C
ox
formed over the gate oxide, which is connected in series to a second parasitic capacitor C
depl
formed over a depletion layer underneath the gate oxide layer. The gate-to-drain capacitance as a total capacitance over these two parasitic capacitors is:
Cgd
=(
C
ox
C
depl
)/[
C
ox
+C
depl
] (1)
Where the capacitance of the parasitic capacitor over a depletion layer is inversely proportional the thickness of the depletion layer t
depl
where a positive bias voltage is applied between drain and gate.
C
depl
=K/t
depl
(2)
Where K is a constant. The thickness of the depletion layer t
depl
is inversely proportional to the square root of the dopant concentration, therefore:
C
depl
=K
(
N
epi
)
1/2
(3)
Where N
epi
represents the dopant concentration of the source epitaxial region
15
. It can be derived from Equations (3) that by reducing the dopant concentration of the epitaxial layer, i.e., N
epi
the capacitance over the depletion layer C
epi
is reduced. And, from Equation (2), it is also clear that the gate-to-drain capacitance C
GD
is also reduced. A relationship between the capacitance C
GD
and that of the N
epi
is shown in
FIG. 1C. A
technique to improve the device switching speed is to reduce the dopant concentration in the N
epi
layer. However, a lower dopant concentration under the gate often causes the on-resistance to increase. Also, if the profile of the doping concentration in the epitaxial layer is not precisely controlled, it may also cause the threshold voltage to increase. For these reasons, improvement of switching speed cannot easily be accomplished by simply lowering the dopant concentration in the depletion layer. As will be further discussed below, the difficulties are due to the lack of control in depth and width of this low dopant concentration region. Improvements in device switching speed are often provided, in several of prior art device as described below, by degrading other performance characteristics.
In U.S. Pat. No. 5,016,066, entitled “Vertical Power MOSFET having High Withstand Voltage and High Switching Speed”; Takahashi disclosed a vertical field effect transistor as that shown in
FIG. 2
The transistor includes a source electrode and a gate on the front surface of a semi-conductor substrate. The substrate has a first conductivity type and an electrode on the back surface of the substrate. The semiconductor device of has the structure wherein a connection region
3
a
of the first conductivity type positioned between two channel-forming base regions
4
of a second and opposite conductivity type is formed by a semiconductor layer. The base regions
4
have a higher impurity concentration, eg., p
+
, than the drain region of the first conductivity type, e.g., n−. The surface portion
3
b
of the connection region
3
a
is connected to the channel, which has a lower impurity concentration, e.g., n
−
, than the connection region
3
a
, e.g., n
+
. But the doping concentration is the same as the impurity concentration as the epitaxial layer as that shown in
FIGS. 2B and 2C
Since tis device is formed to have a structure to provide high withstand voltage, this device is useful for making MOSFET Power device operated at more than 500 volts. For a low voltage device operated below 12 to 60 volts, due to a requirement of low resistivity in the epitaxial layer, the device disclosed by Takahashi tend to have a problem of low switching speed. This is due to a structure that region
3
b
has a same low impurity concentration as the epitaxial layer. Therefore, the device is not practically useful for low voltage application.
In a Japanese Patent Application 54-132908, entitled “Insulated Gate Type Field Effect Transistor”, a transistor field effect transistor is formed to decrease the concentration of an electric field and to increase the dielectric resistance. Referring to
FIG. 3
where a gate oxide film is formed on a wall surface of a concave section made up to the drain region. A region that has extremely low concentration of dopant impurities, e.g., n
−
region
210
, is formed in the drain region at a nose of the concave section. In
FIG. 3
, an N− region
202
functioning as a second drain region is grown on an N+ type semiconductor substrate
201
segregated as a first drain on. An N− type region
210
is formed under the groove section
205
. The electric field is eased with this extremely low concentration N− region. The FET transistor is made to resist high voltage wherein the gate oxide layer is protected near the bottom of the groove. The field effect transistor according to
FIG. 3
, however may not be practically useful for several reasons. An extremely low concentration region
210
can cause the on-resistance to increase and adversely impact the device performance. Furthermore, an implant operation to form these extremely low concentration regions
210
is not self-aligned. An effort to increase the cell density by reducing the size of the transistor cells is hindered. More lateral distance between cells has to be allowed to accommodate potential misalignment errors.
Therefore, there is still a need in the art of power device fabrication, particularly for power DMOS design and fabrication, to provide a simplified and improved fabrication process that would resolve these limitations. Specifically, a DMOS manufactured by this new method must provided reduced gate-to-drain capacitance to improved the switching speed. In the meantime, improvement of switching speed, provided by the novel device structure and manufacture method, should not be achieved at a price of degrading or sacrificing other design or performance characteristics.
SUMMARY OF THE PRESENT INVENTION
It is therefore an object of the present invention to provide a new and novel MOSFET cell structure, and fabrication process to form a MOSFET device with reduced gate-to-drain capacitance. Reduction of capacitance of the MOSFET device is accomplished without significantly increasing the on-resistance or the threshold voltage whereby the aforementioned limitations encountered in the prior art can be overcome.
Specifically, it is an object of the present invention to provide a new and improved MOSFET manufacture process and cell structure by performing a high energy body-conductivity-type dopant implant, e.g., boron implant, through the gate layer to form a shallow low-doping concentration region, e.g., an n
−
region, under the gate. The gate-to-drain capacitance is reduced with reduced do
Chaudhari Chandra
Lin Bo-In
Magepower Semiconductor Corp.
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