Switched backgate bias for FET

Details Switched backgate bias for FET Switched backgate bias for FET

1998-11-18

2001-05-15

Santamauro, Jon (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S083000, C326S098000, C327S534000

Reexamination Certificate

active

06232793

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to improvements in semiconductor circuits and MOS-DRAMs, which use fabricated from MOS-FETs.
2. Description of Related Art
FIG. 1
is a circuit diagram showing a complementary MOS inverter used in a conventional semiconductor circuit. Power source potential V
CC
is applied to the source and backgate (substrate) of a pMOS-FET Q
1
, and ground potential VsS is applied to the source and backgate of an nMOS-FET Q
2
. The gates of the FETs Q
1
and Q
2
are connected to form an input node IN, and their drains are connected to form an output node OUT.
The operation of the thus configured complementary MOS inverter will be described below.
When a logic signal of high level (power source potential V
CC
) is inputted to the input node IN, the FET Q
1
is turned off and the FET Q
2
is turned on, so that a logic signal of low level (ground potential V
SS
=0 V) is outputted from the output node OUT through the FET Q
2
.
Conversely, when a logic signal of low level (ground Potential V
SS
=0 V) is inputted from the input node IN, the FET Q
1
is turned on and the FET Q
2
is turned off, so that a logic signal of high level (power source potential V
CC
) is outputted from the output node OUT through the FET Q
1
.
With increasing miniaturization of semiconductor circuits and scaling-down of individual MOS-FETs used in semiconductor circuits, MOS-FET performance has been increasing. More specifically, by making the channel length shorter and by reducing the gate oxide thickness and thereby reducing the magnitude of the threshold voltage, higher switching speeds are achieved.
When the threshold voltage is reduced or the channel length is made shorter for MOS-FETs to achieve higher switching speeds, there arises the problem that the drain and source depletion layers can easily be connected together, causing a punch-through situation where current flows between source and drain even when the channel is not formed. This increases the subthreshold current that flows under weak inversion when the gate voltage is near and below the threshold voltage.
FIG. 2
is a cross-sectional view schematically showing a conventional memory cell structure for a MOS-DRAM. An nMOS-FET
53
and a capacitor
50
are formed on a p-well
52
. The gate
54
of the FET
53
is connected to a word line WL, the drain
56
is connected to a bit line BL, and the source
55
is connected to one electrode of the capacitor
50
whose other electrode is connected to a cell plate
51
.
In the memory cell
57
of this structure, when an high level signal is given through the word line WL to the gate
54
, the FET
53
conducts and the capacitor
50
is charged/discharged through the source
55
, drain
56
, and bit line BL, to perform a write or refresh operation/read operation.
In the memory cell
57
, however, the charge stored on the capacitor
50
continuously leaks away. This leakage is caused because of subthreshold leakage through the channel of the FET
53
shown by an arrow
58
or junction leakage at the p-n junction shown by an arrow
59
. When peripheral circuitry and the bit line BL are in the standby state, the junction leakage is the main cause; when peripheral circuitry and the bit line BL are in the active state, the sub-threshold leakage is the main cause.
In the MOS-DRAM, refreshing (rewriting) is performed to refresh the stored contents to compensate for the loss due to the above leakage of the memory cell
57
. There are two types of refresh: pause refresh that is performed when the peripheral circuitry and the bit line BL are in the standby state, and disturb refresh that is performed when the peripheral circuitry and the bit line BL are in the active state. As the leakage increases, the refresh cycle must be made shorter to perform refresh with higher frequency.
When the substrate potential (p-well potential) of the FET
53
, which is usually a negative potential, is reduced in magnitude to reduce the junction leakage, the magnitude of the threshold voltage for the FET
53
decreases and the junction leakage is reduced. This, however, causes the problem that the subthreshold leakage increases.
In “MT(Multi-Threshold)-CMOS: 1V High-Speed CMOS Digital Circuit Technology, 1994, The Institute of Electronics, Information and Communication Engineers Spring Convention, C-627,5-195” and “1V High-Speed Digital Circuit Technology with 0.5 &mgr;m Multi-Threshold(MT) CMOS, (Proc. IEEE ASIC Conf., 1993, pp. 186-189)”, there is disclosed a CMOS circuit constructed with pMOS and nMOS FETs having two kinds of threshold voltages, a high threshold voltage and a low threshold voltage. The CMOS circuit using the MT-MOS technology is intended to reduce the subthreshold current that flows during standby state and to increase operating speeds in active state. The circuit construction is as follows. The logic circuit is constructed with low-threshold voltage (0.3 to 0.4 V) FETs. The power supply line and secondary power supply line are connected via a high-threshold voltage (0.7 V) FET that is used to shut off the leak path. Further, the ground line and secondary ground line are connected via another high-threshold voltage (0.7 V) FET. The logic circuit is connected between the secondary power supply line and the secondary ground line.
FIG. 3
is a circuit diagram showing a CMOS circuit using the MT-MOS technology in which the logic circuit is composed of an inverter array. The gates of a pMOS-FET Q
51
and nMOS-FET Q
52
in an inverter I
5
are connected to form an input node IN, while the node between the drains of the pMOS-FET Q
51
and nMOS-FET Q
52
is connected to the node between the gates of a pMOS-FET Q
53
and nMOS-FET Q
54
in an inverter I
6
. Likewise, the node between the drains of the pMOS-FET Q
53
and nMOS-FET Q
54
is connected to the node between the gates of a pMOS-FET Q
55
and nMOS-FET Q
56
in an inverter I
7
, while the node between the drains of the pMOS-FET Q
55
and nMOS-FET Q
56
is connected to the node between the gates of a pMOS-FET Q
57
and nMOS-FET Q
58
in an inverter I
8
. The drains of the PMOS-FET Q
57
and nMOS-FET Q
58
are connected to form an output node OUT.
The sources of the pMOS-FETs Q
51
, Q
53
, Q
55
, and Q
57
are connected to a secondary power supply line V
CC1
, while the sources of the nMOS-FETs Q
52
, Q
54
, Q
56
, and Q
58
are connected to a secondary ground line V
SS1
. The secondary power supply line V
CC1
is connected to a power supply line V
CC
(power source potential: V
CC
) via a pMOS-FET Q
59
whose gate is supplied with an inverted clock signal #ø. The secondary ground line V
SS1
is connected to a ground line V
SS
(ground potential: V
SS
) via an nMOS-FET Q
60
whose gate is supplied with a clock signal ø. The threshold voltage of the FETs Q
59
and Q
60
is larger than that of the FETs Q
51
, Q
52
, Q
53
, Q
54
, Q
55
, Q
56
, Q
57
, and Q
58
that form the inverters I
5
, I
6
, I
7
, and I
8
.
For the inverter array using the MT-MOS-FETs, the FETs Q
59
and Q
60
are caused to conduct in active state. As a result, the power source potential V
CC
is given to the sources of the pMOS-FETs Q
51
, Q
53
, Q
55
, and Q
57
via the secondary power supply line V
CC1
, while the sources of the nMOS-FET Q
52
, Q
54
, Q
56
, and Q
58
are supplied with the ground potential V
SS
via the secondary ground line V
SS1
.
In standby state, on the other hand, the FETs Q
59
and Q
60
are nonconducting. This disconnects the secondary power supply line V
CC1
from the power source potential V
CC
and the secondary ground line V
SS1
from the ground potential V
SS
. As a result, the current path between the power supply and ground is cut off, and therefore, the subthreshold current is reduced. The low threshold voltage of the FETs Q
51
, Q
52
, Q
53
, Q
54
, Q
55
, Q
56
, Q
57
, and Q
58
that form the inverters I
5
, I
6
, I
7
, and I
8
allows high-speed operations during active state. However, since the subthreshold current flows through the inverter array during standby state,

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