Switch/network adapter port for clustered computers...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C710S062000, C710S105000, C709S250000, C370S463000

Reexamination Certificate

active

09932330

ABSTRACT:
A switch
etwork adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

REFERENCES:
patent: 4783730 (1988-11-01), Fischer
patent: 4972457 (1990-11-01), O'Sullivan
patent: 5230057 (1993-07-01), Shido et al.
patent: 5673204 (1997-09-01), Klingelhofer
patent: 5889959 (1999-03-01), Whittaker et al.
patent: 5892962 (1999-04-01), Cloutier
patent: 5903771 (1999-05-01), Sgro et al.
patent: 5915104 (1999-06-01), Miller
patent: 5923682 (1999-07-01), Seyyedy et al.
patent: 6026478 (2000-02-01), Dowling et al.
patent: 6047343 (2000-04-01), Olarig et al.
patent: 6052134 (2000-04-01), Foster
patent: 6052773 (2000-04-01), DeHon et al.
patent: 6076152 (2000-06-01), Huppenthal et al.
patent: 6108730 (2000-08-01), Dell et al.
patent: 6148356 (2000-11-01), Archer et al.
patent: 6192439 (2001-02-01), Grunewald et al.
patent: 6202111 (2001-03-01), Wallach et al.
patent: 6295571 (2001-09-01), Scardamalia et al.
patent: 6326973 (2001-12-01), Behrbaum et al.
patent: 6452700 (2002-09-01), Mays, Jr.
patent: 6480014 (2002-11-01), Li et al.
patent: 6581157 (2003-06-01), Chiles et al.
patent: 6598199 (2003-07-01), Tetrick
patent: 6633945 (2003-10-01), Fu et al.
patent: 6799252 (2004-09-01), Bauman
patent: 0 571 099 (1993-11-01), None
patent: 59-206972 (1984-11-01), None
patent: 63-086079 (1988-04-01), None
Fiscal 1994 Project Portfolio Report, Duane Northcutt, Sun Microsystem, www.research.sun.com/techrep/1994/annualreport94/tcm.html, pp. 1-3.
Yun, Hyun-Kyu and Silverman, H. F.; “A distributed memory MIMD multi-computer with reconfigurable custom computing capabilities”, Brown University, Dec. 10-13, 1997, pp. 7-13.
Agarwal, A., et al., “The Raw Compiler Project”, pp. 1-12, http://cag-www.lcs.mit.edu/raw, Proceedings of the Second SUIF Compiler Workshop, Aug. 21-23, 1997.
Albaharna, Osama, et al., “On the viability of FPGA-based integrated coprocessors”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 206-215.
Amerson, Rick, et al., “Teramac—Configurable Custom Computing”, © 1995 IEEE, Publ. No. 0-8186-7086-X/95, pp. 32-38.
Barthel, Dominique Aug. 25-26, 1997, “PVP a Parallel Video coProcessor”, Hot Chips IX, pp. 203-210.
Bertin, Patrice, et al., “Programmable active memories: a performance assessment”, © 1993 Massachusetts Institute of Technology, pp. 88-102.
Bittner, Ray, et al., “Computing kernels implemented with a wormhole RTR CCM”, © 1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 98-105.
Buell, D., et al. “Splash 2: FPGAs in a Custom Computing Machine—Chapter 1—Custom Computing Machines: An Introduction”, pp. 1-11, http://www.computer.org/espress/catalog/bp07413/spls-ch1.html (originally b lieved published in J. of Supercomputing, vol. IX, 1995, pp. 219-230.
Casselman, Steven, “Virtual Computing and The Virtual Computer”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 43-48.
Chan, Pak, et al., “Architectural tradeoffs in field-programmable-device-based computing systems”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 152-161.
Clark, David, et al., “Supporting FPGA microprocessors through retargetable software tools”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 195-103.
Cuccaro, Steven, et al., “The CM-2X: a hybrid CM-2/Xilink prototype”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 121-130.
Culbertson, W. Bruce, et al., “Exploring architectures f r volume visualizati n n th Teramac custom computer”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 80-88.
Culbertson, W. Bruce, et al., “Def ct t l rance n the Teramac custom computer”, © 1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 116-123.
Dehon, Andre, “DPGA-Coupled microprocessors: commodity IC for the early 21stcentury”, © 1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 31-39.
Dehon, A., et al., “MATRIX A Reconfigurable Computing Device with Configurable Instruction Distribution”, Hot Chips IX, Aug. 25-26, 1997, Stanford, California, MIT Artificial Intelligence Laboratory.
Dhaussy, Philippe, et al., “Global control synthesis for an MIMD/FPGA machine”, © 1994 IEEE, Publ. N . 0-8186-5490-2/94, pp. 72-81.
Elliott, Duncan, et al., “Computational Ram: a memory-SIMD hybrid and its application to DSP”, © 1992 IEEE, Publ. No. 0-7803-0246-X/92, pp. 30.6.1-30.6.4.
Fortes, Jose, et al., “Systolic arrays, a survey of seven projects”, © 1987 IEEE, Publ. No. 0018-9162/87/0700-0091, pp. 91-103.
Gokhale, M., et al., “Processing in Memory: The Terasys Massively Parallel PIM Array” © Apr. 1995, IEEE, pp. 23-31.
Gunther, Bernard, et al., “Assessing Document Relevance with Run-Time Reconfigurable Machin s”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 10-17.
Hagiwara, Hiroshi, et al., “A dynamically microprogrammable computer with low-level parallelism”, © 1980 IEEE, Publ. No. 0018-9340/80/07000-0577, pp. 577-594.
Hartenstein, R. W., et al. “A General Approach in System Design Integrating Reconfigurable Accel rators,” http://xputers.informatik.uni-kl.de/papers/paper026-1.html, IEEE 1996 Conference, Austin, TX, Oct. 9-11, 1996.
Hartenstein, Reiner, et al., “A reconfigurable data-driven ALU for Xputers”, © 1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 139-146.
Hauser, John, et al.: “GARP: a MIPS processor with a reconfigurable co-processor”, © 1997 IEEE, Publ. No. 0-08186-8159-4/97, pp. 12-21.
Hayes, John, et al., “A microprocessor-based hypercube, supercomputer”, © 1986 IEEE, Publ. No. 0272-1732/86/1000-0006, pp. 6-17.
Herpel, H. -J., et al., “A Reconfigurable Computer for Embedded Control Applications”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 111-120.
Hogl, H., et al., “Enable++: A second generation FPGA processor”, © 1995 IEEE, Publ. No. 0-8186-7086-X/95, pp. 45-53.
King, William, et al., “Using MORRPH in an industrial machine vision system”. © 1996 IEEE, Publ. No. 08186-7548-9/96, pp. 18-26.
Manohar, Swaminathan, et al., “A pragmatic approach to systolic design”, © 1988 IEEE, Publ. No. CH2603-9/88/0000/0463, pp. 463-472.
Mauduit, Nicolas, et al., “Lneuro 1.0: a piece of hardware LEGO for building neural network systems,” © 1992 IEEE, Publ. No. 1045-9227/92, pp. 414-422.
Mirsky, Ethan A., “Coarse-Grain Reconfigurable Computing”, Massachusetts Institute of Technology, Jun. 1996.
Mirsky, Ethan, et al., “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 157-166.
Morley, Robert E., Jr., et al., “A Massively Parallel Systolic Array Processor System”, © 1988 IEEE, Publ. N . CH2603-9/88/0000/0217

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Switch/network adapter port for clustered computers... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Switch/network adapter port for clustered computers..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Switch/network adapter port for clustered computers... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3910624

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.