Switch block for FPGA architectures

Details Switch block for FPGA architectures Switch block for FPGA architectures

2006-10-02

2008-12-09

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S098000

Reexamination Certificate

active

07463067

ABSTRACT:
A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.

REFERENCES:
patent: 6768338 (2004-07-01), Young et al.
patent: 6798270 (2004-09-01), Bauer
patent: 6949951 (2005-09-01), Young et al.
patent: 7215141 (2007-05-01), Lewis
patent: 2004/0008056 (2004-01-01), Kursun et al.
patent: 2005/0007153 (2005-01-01), Ding et al.
patent: 2007/0085563 (2007-04-01), Ciccarelli et al.
patent: 2007/0279088 (2007-12-01), Ciccarelli et al.
Anderson et al., Active Leakage Power Optimization for FPGAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Mar. 2006, pp. 423-437, vol. 25, No. 3.
Rahman et al., Evaluation of Low-Leakage Design Techniques for Field Programmable Gate Arrays, FPGA'04, Feb. 22-24, 2004, pp. 23-30, 2004, Monterey, California.
Wei et al., Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits, DAC 98, Jun. 15-19, 1998, pp. 489-494, San Francisco, California.
Lodi et al., A Pipelined Configurable Gate Array for Embedded Processors, FPGA'03, Feb. 23-25, 2003, pp. 21-30, Monterey, California.

Affiliated with

Also associated with

Rating

Switch block for FPGA architectures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Switch block for FPGA architectures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Switch block for FPGA architectures will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4047633