Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-04-16
2004-05-18
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S381000
Reexamination Certificate
active
06737313
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of semiconductor manufacture and, more particularly, to the formation of a ruthenium metal layer during the formation of a semiconductor device.
BACKGROUND OF THE INVENTION
During the manufacture of semiconductor devices such as dynamic random access memories (DRAMs), microprocessors, and logic devices, several conductive structures are commonly formed. For example, transistor gates and capacitor bottom (storage) and top plates, typically manufactured from doped polysilicon, and interconnects and runners, typically formed from aluminum and/or copper, are formed on various types of devices.
A design goal of semiconductor engineers is to decrease feature sizes while maintaining adequate conductivity of interconnects and sufficient capacitance within storage capacitors. With increasing device density, polysilicon becomes less desirable as a material to form conductive structures such as storage capacitors and other conductive features. A conductive material which has been used for various semiconductor device structures such as capacitor plates in ferroelectrics devices is ruthenium oxide (RuO
2
). Ruthenium oxide exhibits good step coverage and a uniform thickness across various topographies. However, RuO
2
is not stable and disproportionates into a strong oxidizer. It will, over time, oxidize various metal layers which are in close proximity. For example, if RuO
2
is used as a capacitor bottom plate, it will oxidize a titanium nitride or tungsten nitride top plate through a tantalum pentoxide (Ta
2
O
5
) capacitor dielectric. Further, a barrier layer must be formed to protect a polysilicon contact pad from the RuO
2
, as the RuO
2
will oxidize the polysilicon and result in a bottom plate being electrically isolated from the contact pad by a silicon dioxide layer.
Attempts have also been made to use ruthenium metal as capacitor plates or as various other structures, as ruthenium metal is stable and is easily planarized during chemical mechanical polishing (CMP). However, previous methods for forming a ruthenium metal layer, for example using chemical vapor deposition (CVD), result in a layer which has poor adhesion to an underlying silicon dioxide layer.
Various layers have been proposed to enhance the adhesion of a metal layer to a dielectric. The following U.S. patents, each having at least one inventor in common with the present application and assigned to Micron Technology, Inc., are each incorporated herein as if set forth in its entirety. Each patent describes the use of adhesion layers: U.S. Pat. Nos. 5,990,559; 6,197,628; 6,204,172, 6,218,297; 6,281,161; 6,284,655; 6,323,511; 6,403,414; 6,421,223; 6,461,909; 6,462,367; 6,495,458. In particular, U.S. Pat. No. 6,462,367 discloses in one embodiment an adhesion layer for adhering ruthenium to a dielectric, the adhesion layer comprising RuSi
x
O
y
, where “x” and “y” are in the range of about 0.01 to about 10, with a thickness of between about 10 angstroms (Å) to about 1,000 Å.
While an adhesion layer is often desired or required to ensure a device does not malfunction as a result of a layer (such as ruthenium metal) peeling from an underlying layer (such as a silicon dioxide dielectric), the functionality of some completed structures is enhanced if the distance between two layers is minimized. Thus, the inclusion of an extra layer, the adhesion layer, between two such layers can be detrimental. Further, adding additional layers to a complicated process can introduce additional variation which may result in decreased device performance or predictability of device functionality.
A method for forming a ruthenium metal layer on a dielectric layer which reduces or eliminates the problems described above, and the structure resulting from the method, would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a new method which, among other advantages, reduces problems associated with the manufacture of semiconductor devices, particularly problems resulting from the failure of a ruthenium metal layer to adhere to a dielectric layer, and problems resulting from thickness and electrical variations introduced by an adhesion layer. In accordance with one embodiment of the invention, a dielectric layer is formed, then etched if necessary to form a desired supporting dielectric feature. Subsequently, the exposed surface of the dielectric layer is treated by exposure to silane (SiH
4
). After this treatment, a ruthenium metal layer is formed, for example using chemical vapor deposition. Treating the dielectric layer with silane prior to forming the ruthenium metal layer has been found to provide enhanced adhesion between the ruthenium metal layer and the dielectric layer without adding an additional adhesion layer between the dielectric and ruthenium layers.
While treating silicon dioxide with silane may be preferred, it is also possible to treat the silicon dioxide with other chemicals, such as other silicon-containing gasses. For example, silicon hydrides (compounds of the general formula Si
n
H
2n+2
) other than silane, such as disilane gas (Si
2
H
6
) or methylated silanes, may function sufficiently to alter the surface termination of the silicon dioxide. As described in the Detailed Description of the Preferred Embodiment, it is also possible to treat oxides other than silicon dioxide.
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Kraus Brenda D.
Marsh Eugene P.
Martin Kevin D.
Micro)n Technology, Inc.
Tsai H. Jey
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