Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-05-27
2008-05-27
Gurley, Lynne (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S283000, C438S303000, C438S305000, C257S328000, C257S135000, C257S339000, C257S341000, C257S342000, C257SE29257
Reexamination Certificate
active
11304196
ABSTRACT:
Methods and apparatus are provided for TMOS devices, comprising multiple N-type source regions, electrically in parallel, located in multiple P-body regions separated by N-type JFET regions at a first surface. The gate overlies the body channel regions and the JFET region lying between the body regions. The JFET region communicates with an underlying drain region via an N-epi region. Ion implantation and heat treatment are used to tailor the net active doping concentration Ndin the JFET region of length Laccand net active doping concentration Nain the P-body regions of length Lbodyso that a charge balance relationship (Lbody*Na)=k1*(Lacc*Nd) between P-body and JFET regions is satisfied, where k1is about 0.6≦k1≦1.4. The entire device can be fabricated using planar technology and the charge balanced regions need not extend through the underlying N-epi region to the drain.
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Baird Robert W.
de Fresart Edouard D.
Qin Ganming
Belousov Alexander
Freescale Semiconductor Inc.
Gurley Lynne
Ingrassia Fisher & Lorenz P.C.
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