Superjunction device and process for its manufacture

Details Superjunction device and process for its manufacture Superjunction device and process for its manufacture

2005-07-19

2005-07-19

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

C438S136000, C438S186000, C438S192000

Reexamination Certificate

active

06919241

ABSTRACT:
A process to make a low voltage (under 200 volts) superjunction device employs spaced P type implants into the generally central depth region of an epitaxially formed N layer. The wafer is then placed in a diffusion furnace and the spaced implants are driven upward and downward by 4 to 8 microns to form spaced P pylons in an N type epitaxial body. MOSgated structures are then formed atop each of the P pedestals. The total P charge of each pedestal is at least partially matched to the total N charge of the surrounding epitaxial material. The initial implant may be sandwiched between two discrete epitaxial layers.

REFERENCES:
patent: 6204153 (2001-03-01), Gardner et al.
patent: 6611021 (2003-08-01), Onishi et al.

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