Super-self-aligned trench-dmos structure and method

Details Super-self-aligned trench-dmos structure and method Super-self-aligned trench-dmos structure and method

2011-01-11

2011-01-11

Hoang, Quoc D (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21418

Reexamination Certificate

active

07867852

ABSTRACT:
A semiconductor device includes a P-body layer formed in an N-epitaxial layer; a gate electrode formed in a trench in the P-body and N-epitaxial layer; a top source region formed from the P-body layer next to the gate electrode; a gate insulator disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the N-epitaxial layer; a cap insulator disposed on top of the gate electrode; and an N+ doped spacer disposed along a sidewall of the source and a sidewall of the gate insulator. The source includes N+ dopants diffused from the spacer. A body contact region containing P-type dopants is formed from the N-epitaxial layer. The contact region touches one or more P-doped regions of the P-body layer and the source. Methods for manufacturing such a device are also disclosed. Embodiments of this invention may also be applied to P-channel devices.

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U.S. Appl. No. 12/958,162, entitled “Super-Self-Aligned Trench-DMOS Structure and Method”, filed Dec. 1, 2010.

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