Super halo implant combined with offset spacer process

Details Super halo implant combined with offset spacer process Super halo implant combined with offset spacer process

1999-12-20

2001-09-25

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S305000

Reexamination Certificate

active

06294432

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for forming integrated circuits, and more particularly to a method for forming semiconductor device by using super halo implant combined with offset spacer process.
2. Description of the Prior Art
As MOS (Metal-Oxide-Semiconductor) device scaled down to sub-0.25 &mgr;m, in order to maintain enough short channel margin, tilt angle halo implant is necessary. Unfortunately, the poly spacing is also shrunk, it dose strictly limit halo tilt angle. Thus, super halo process has been proposed. Super halo process uses zero angle halo implant after poly has been defined, then lateral diffusion is performed by using thermal anneal. Following description will set forth an exemplary process of super halo process with the aid of
FIG. 1A
to FIG.
1
D.
Referring to
FIG. 1A
, a substrate
100
is provided with gate oxide layer
120
and poly gate
130
formed thereon. Thus, two gate electrodes formed in an active area defined in between the isolation regions (not shown in the FIGURE). The gate oxide layer
120
is a layer of insulation to separate poly gate
130
and substrate
100
. Source and drain regions will be formed in the substrate
100
at opposite ends of the gate
130
. A channel region under the gate electrode
130
is located between the source and drain regions in the substrate
100
. Then, super halo implant is preformed to form implant regions
112
, as shown in FIG.
1
B. The implant regions
112
in the substrate
100
are placed to completely separate the source and drain regions from the channel regions for improving short channel effect. The implant step needs to be performed twice, one for NMOS and the other for PMOS, and then two masks and lithography processes are applied. After the super halo implant steps, such as anneals, cause the halo dopant diffuse toward the channel region.
Subsequently, as shown in
FIG. 1C
, another implant occurs. This implant step is to form source/drain extension regions
114
. The amount of dopant is controlled so that the dopant concentration is relatively low to source and drain regions, and the junction depth is controlled relative shallow to source/drain regions. Then, a thermal anneal is performed so that the dopant diffuses toward the area under gate electrode
130
and the gate to drain overlap will increase. Then, spacer
122
is formed on the sidewall of the gate
130
, and again another implant is performed to form source/drain regions
116
, as shown in FIG.
1
D. The processes which follow are salicide process and backend process.
By the way, the formulation of source/drain extension region and super halo implant must be separated because of shallow junction issue. It means that the super halo process needs to increase two mask steps (one for NMOS and the other for PMOS).
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming semiconductor devices that substantially combines super halo implant and offset spacer process. The super halo process in the present invention provides more lateral diffusion by combining offset spacer and can obtain better device performance for shorter channel margin.
It is another object of this invention that super halo anneal can be replaced by offset spacer deposition temperature. Thus, the thermal cycle can be reduced.
It is a further object of this invention to reduce the gate to drain overlap region to improve device performance in offset spacer process.
In one embodiment, a method for forming a metal-oxide-semiconductor device by using super halo combined with offset spacer process is disclosed. The method includes first providing a substrate having a gate electrode formed thereon and a halo implant region formed therein. Secondly, a dielectric layer is deposited on the substrate and the gate electrode. Thirdly, anneal is performed so that dopant of halo implant will diffuse. Fourth, the dielectric layer is anisotropically etched to form an offset spacer. Fifth, source/drain extension regions are formed. Finally, a spacer is formed on the sidewall of the offset spacer beside the gate electrode, and source/drain regions are formed in the substrate.


REFERENCES:
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patent: 5595919 (1997-01-01), Pan
patent: 5736446 (1998-04-01), Wu
patent: 5759901 (1998-06-01), Loh et al.
patent: 5930615 (1999-07-01), Manning
patent: 6046472 (2000-04-01), Ahmad et al.
patent: 6049114 (2000-04-01), Maiti et al.
patent: 6051458 (2000-04-01), Liang et al.
patent: 6083783 (2000-07-01), Lin et al.
patent: 6190981 (2001-02-01), Lin et al.

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