Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-06
2002-03-12
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S213000, C438S589000, C438S157000
Reexamination Certificate
active
06355532
ABSTRACT:
This invention relates to field effect transistors (FETs) formed in complimentary metal oxide semiconductor (CMOS) integrated circuits (ICs). More particularly, the present invention relates to a new and improved planar FET having a short-length and vertically-oriented channel structure interdigitated with a dual-gate structure to obtain fully-depleted and fully-inverted channel operating and conductivity characteristics. Moreover, the present invention relates to fabricating such an improved FET using conventional CMOS fabrication techniques, including photolithographic techniques which are incapable themselves of achieving structural widths as small as required for the FET to obtain the fully-depleted and fully-inverted channel operating and conductivity characteristics.
BACKGROUND OF THE INVENTION
During the two decades preceding this invention, the continual evolution of semiconductor technology has seen the size or topology of transistors shrink by about half at regular time intervals of approximately 18 months. As a result, the density of FETs in comparably-sized ICs has doubled that the same rate. It is predicted that this doubling effect will reach a point where physics and economics can no longer support such increases in density, and may reach proportions where no further density increases will be possible by using the presently-preferred, conventional planar CMOS fabrication techniques.
Conventional CMOS FETs are typically formed in a structural configuration referred to as “planar” because the various regions of the FET are formed in patterns established in a horizontal plane. For example, the source and drain regions are formed as horizontal planar structures extending downward into a substrate from an upper horizontal surface. Similarly, the channel structure of the FET, which extends between the source and drain regions, is also formed as a horizontal planar structure. The gate structure extends as a generally planar layer of material formed on top of the channel structure. Although all of these regions and components have a vertical dimension, the majority of their influence in the FET is achieved because of the horizontal extent of their regions and structures. The typical CMOS fabrication technique utilizes these planar configurations because they are easily fabricated in a horizontal plane using conventional techniques which are directed vertically downward onto the substrate or other structures formed on top of the substrate.
The planar aspects of the conventional CMOS structures have been recognized as a significant limitation on the continually diminishing size evolution in CMOS FETs. For example, as the size of the source, drain, channel and gate regions are reduced in the horizontal plane, the length of the channel becomes shorter, placing the source and drain regions in closer proximity with one another. This closer proximity diminishes the ability of the gate structure to control conductivity through the channel, and hence the conductivity of the FET itself. These adverse influences on the conductivity characteristics of the FET are referred to as short channel effects.
Short channel effects are explained as follows. Conductivity through the channel is controlled by a vertical electric field created by the gate voltage in a direction perpendicular to the flow of current in the channel. However, an electric field is also created by the charged source and drain regions. The source and drain fields encroach laterally onto the channel. As the channel length shortens, the lateral drain and source fields have a greater influence on the channel conductivity characteristics. With a sufficiently short channel, the lateral source and drain fields can cause the gate field to lose control over the FET conductivity, even to the extent of creating a short between the source and the drain, thus diminishing or destroying the operating characteristics of the FET.
Shrinking the size of the FET structure also requires reducing the size of the gate oxide and source and drain regions, thus creating the requirement that the power supply voltage must also be reduced to maintain gate oxide integrity and junction breakdown margins to prevent wear out due to voltage stress and diminished lifetime resulting from hot carrier injection. Reducing the voltage of the power supply creates semiconductor package and circuit board-level design problems to accommodate multiple different power supply voltage levels. Such requirements increase the cost of semiconductor fabrication as well as future costs of developing technology.
FET structures which are alternatives to planar structures have been conceived as partial solutions to the diminishing size problems. One such structure is a dual-gate structure. In general, a dual-gate structure involves placing a gate on opposite sides of the channel. Because both sides of the channel are thereby subjected to the gate field, rather than the single side of the channel in a conventional planar FET structure, the gate will maintain a predominant field affect over the lateral fields from the source and drain even when the length of the channel is reduced. The difficulty with dual-gate FET structures is that they are very difficult to manufacture. The manufacturing difficulties have prevented dual-gate FETs from achieving a significant level of commercial acceptability.
One type of dual-gate FET involves a “gate-all-around” configuration. The gate-all-around configuration is created by forming a cavity beneath a silicon channel structure by an isotropic etch. After gate oxidation, the cavity under the channel silicon structure is under-filled by polysilicon which is deposited by chemical vapor deposition. Thereafter, gate material is placed over the top of the channel silicon structure and in contact with the under-filled material in the cavity. The resulting gate structure completely surrounds the silicon channel structure, thereby causing the gate to completely encircle the channel. Ends of the channel structure become the source and drain. The gate-all-around fabrication process is very complex and difficult to execute on a reliable and consistent basis.
Another method of forming a gate-all-around MOSFET structure provides for forming a tunnel of the gate material. The source, channel and drain are then created by epitaxially growing silicon through the preformed tunnel.
Another type of a dual-gate FET is called a “delta” configuration. The delta configuration involves forming a generally rectangular wall of silicon which extends vertically upward from the substrate, positioning the rectangular wall on a narrow edge. The vertical extension of the wall is usually formed by eroding or otherwise eliminating areas of the substrate adjacent to the junction of the vertically-extending wall with the substrate. Gate material is thereafter deposited over the sides and top of the wall. A field oxidation process may cause the field oxide to penetrate the bulk silicon at the base of the junction of the wall with the substrate until the field oxide on both sides of the wall junction meet, thereby “pinching off” the channel from the bulk silicon. The gate material surrounds the wall on at least three sides, thereby establishing a gate electric field over most of the silicon structure which forms the channel. Ends of the silicon wall structure which extend out beyond the gate material become the source and drain regions for the FET.
Another type of structure that is similar to the gate-all-around MOSFET is called the “surrounding-gate” MOSFET. A vertical pillar of silicon is surrounded or wrapped by the gate material. The base of the silicon pillar is connected to the substrate, or a structure formed on the substrate, and forms the source. The top of the pillar protrudes out of the surrounding gate material and forms the drain. The pillar of a surrounding-gate MOSFET may be cylindrically or elongated rectangularly shaped in a top view cross section. Fabrication processes may cause the short edges of a rectangular pillar to be rounded. The cylindrical pillar con
Daniel David
Hornback Verne
Seliskar John J.
Estrada Michelle
Fourson George
Ley, L.L.C. John R.
LSI Logic Corporation
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