Substrate topography compensation at mask design: 3D OPC...

Details Substrate topography compensation at mask design: 3D OPC... Substrate topography compensation at mask design: 3D OPC...

2005-05-17

2005-05-17

McPherson, John A. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S030000, C430S396000, C216S038000, C716S030000, C716S030000

Reexamination Certificate

active

06893800

ABSTRACT:
A semiconductor manufacturing method analyzes topography variations in three dimensions for each photolithographic level and determines critical dimension (CD) bias compensation as inputs to mask layout creation. Accurate predictions of topography variation for a specific mask design are made at the die level using known pattern density and CMP planarization length characteristics for a specific pattern. Exhaustive characterization of the photoresist response to de-focus and mask bias is determined by artificially expanding loss of CD through focus. Mask compensation to an expanded range of focus over all lines and spaces is maintained within the specification. 3D mask density data is obtained to determine the height component at each pixel location in the die. The resulting 3D OPC model is then utilized for mask creation.

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