Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-06-21
2008-08-12
Landau, Matthew C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S366000, C257SE29126, C257SE27060, C257SE29127, C257S213000
Reexamination Certificate
active
07411252
ABSTRACT:
Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate. A trench isolation structure extending through the polysilicon layer to the insulator layer isolates current flowing through the polysilicon layer from other devices on the silicon substrate.
REFERENCES:
patent: 5646900 (1997-07-01), Tsukude et al.
patent: 5917199 (1999-06-01), Byun et al.
patent: 6211533 (2001-04-01), Byun et al.
patent: 6248626 (2001-06-01), Kumar et al.
patent: 6251716 (2001-06-01), Yu
patent: 6433609 (2002-08-01), Voldman
patent: 6445032 (2002-09-01), Kumar et al.
patent: 6534822 (2003-03-01), Xiang et al.
patent: 6580119 (2003-06-01), Hsieh
patent: 6611023 (2003-08-01), En et al.
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6664598 (2003-12-01), Dennard et al.
patent: 6674672 (2004-01-01), Forbes et al.
patent: 6756607 (2004-06-01), Yamashita et al.
patent: 6759308 (2004-07-01), Xiang et al.
patent: 6764884 (2004-07-01), Yu et al.
patent: 2004/0000692 (2004-01-01), Yamashita et al.
patent: 2004/0036126 (2004-02-01), Chau et al.
patent: 2004/0036127 (2004-02-01), Chau et al.
patent: 2004/0094807 (2004-05-01), Chau et al.
patent: 2004/0145000 (2004-07-01), An et al.
patent: 2004/0217430 (2004-11-01), Chu
patent: 2005/0035415 (2005-02-01), Yeo et al.
patent: 2005/0073005 (2005-04-01), Nowak et al.
patent: WO 2004/019414 (2004-03-01), None
patent: WO 2004053996 (2004-06-01), None
patent: WO 2004068571 (2004-08-01), None
Heyn, et al., “Design and Analysis of New Protection Structures for Smart Power Technology With Controlled Trigger and Holding Voltage,” 6 pages.
Anderson Brent A.
Breitwisch Matthew J.
Nowak Edward J.
Gibb & Rahman, LLC
International Business Machines - Corporation
Kim Jay
Landau Matthew C.
LandOfFree
Substrate backgate for trigate FET does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Substrate backgate for trigate FET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Substrate backgate for trigate FET will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4015621