Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-12-03
2003-05-27
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S612000
Reexamination Certificate
active
06569758
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to interconnect techniques in an integrated circuit device, and more particularly, to a very low resistivity interconnection method and structure using bonded metal wires.
(2) Description of the Prior Art
Internal interconnects of integrated circuit devices are typically formed using metal films that have been deposited and patterned. These metal films provide low resistivity connections between the various active and passive devices and layers in the circuit. In certain applications, such as high power devices, the resistivity of the metal film lines is too large.
Referring now to
FIG. 1
, an exemplary prior art integrated circuit is illustrated in cross section. In this example, two MOS transistors
34
and
38
are formed on a substrate
10
. The transistors
34
and
38
have source/drain regions A, B, and C
14
comprising a patterned diffusion layer
14
in the substrate
10
. In this example, the circuit requires that source/drain regions A and B be coupled together through a low resistivity path while region C is not connected to A and B. To form the coupling path, a first metal layer
22
contacts the source/drain regions
14
. A second metal layer
30
contacts the first metal layer
22
and couples region A to region B via the bridge
54
of second metal layer
30
. A first metal layer section
50
contacts the C region.
Referring now to
FIG. 2
, a simplified model of the prior art example circuit is shown. The model shows the coupling metals sections as resistors R
METAL1
50
and R
METAL2
54
. The resistance between nodes A and B is the resistance of the first and second metal paths including the bridge
54
. This resistance R
METAL2
54
depends on the resistivity characteristics of the deposited metal film. If the resistance is too high, it can only be made lower by increasing the width of the metal connection. However, space limitations on the circuit die restrict the metal size. In addition, the presence of the C region eliminates the use of the first metal layer as a parallel interconnect path for A and B. In a high power application, where a large current flow may cause a large IR drop, the integrated circuit process may not be capable of creating an interconnect of low enough resistance using the available metal film layers.
Several prior art inventions describe the application of bonded wire to integrated circuit devices. U.S. Pat. No. 5,032,889 to Murao et al describes a wafer-scale integrated circuit device where functional blocks on the wafer are interconnected using a combination of metal layer lines on the IC and bonding wires to thereby improve reliability. U.S. Pat. No. 5,869,357 to Zambrano discloses a metallization and wire bonding process for a power semiconductor device.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method for forming a low resistivity interconnection in an integrated circuit device.
A further object of the present invention is to provide a method to reduce interconnect resistivity while using a minimum of circuit area.
A still further object of the present invention is to reduce interconnect resistivity by bonding metal wire or stitches to the uppermost metal interconnect layer.
A yet still further object of the present invention is to combine multiple bonded metal wire interconnects with multiple conductive layers to minimize resistivity.
Another object of the present invention is to provide a low resistivity structure for connecting diffusion regions, such as MOS source/drain regions.
In accordance with the objects of this invention, a method to form a very low resistivity interconnection in the manufacture of an integrated circuit device is achieved. A bottom conductive layer is formed overlying a substrate. The bottom conductive layer creates a first electrical coupling of a first location and a second location of the integrated circuit device. A dielectric layer is formed overlying the bottom conductive layer. A top conductive layer is formed overlying the dielectric layer. The top conductive layer is coupled to the bottom conductive layer through openings in the dielectric layer such that the top conductive layer creates a second electrical coupling of the first location and the second location. A metal wire is bonded to the top conductive layer such that the metal wire creates a third electrical coupling of the first location and the second location to complete the very low resistivity interconnection in the manufacture of the integrated circuit device.
Also in accordance with the objects of the present invention, a method to form a very low resistivity interconnection between two source/drain regions in the manufacture of an integrated circuit device us achieved. A plurality of source/drain regions for MOS transistors are formed in a substrate. An insulating layer is formed overlying the substrate. The insulating layer has openings to expose a first source/drain region and a second source/drain region. A conductive layer is formed overlying the insulating layer and contacting the first and second source/drain regions. A metal wire is bonded to the conductive layer such that metal wire creates an electrical coupling of the first and the second source/drain regions to complete the very low resistivity interconnection in the manufacture of the integrated circuit device.
Also in accordance with the objects of the present invention, a low resistivity integrated circuit structure is achieved comprising, first, a diffusion layer in a substrate. The diffusion layer further comprises a first region and a second region. A conductive layer overlies the substrate with an insulating layer therebetween. The conductive layer contacts the first and second regions through openings in the insulating layer. Finally, an electrical coupling exists between the first region and the second region. The electrical coupling comprises a metal wire bonded to the conductive layer.
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patent: 4891333 (1990-01-01), Baba et al.
patent: 5032889 (1991-07-01), Murao et al.
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patent: 5498569 (1996-03-01), Eastep
patent: 5673845 (1997-10-01), Ball
patent: 5869357 (1999-02-01), Zambrano
patent: 6187673 (2001-02-01), Lai et al.
patent: 6384486 (2002-05-01), Zuniga et al.
patent: 6419145 (2002-07-01), Ball
patent: 6444565 (2002-09-01), Feild et al.
patent: 0418802 (1990-09-01), None
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patent: 06061288 (1994-03-01), None
patent: 2000133730 (2000-05-01), None
Jórger Wolfgang
Keller Michael
Stellberger Achim
Ackerman Stephen B.
Dialog Semiconductor GmbH
Jr. Carl Whitehead
Saile George O.
Schillinger Laura M
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