Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-07-07
1999-05-04
Dang, Trung
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438270, 438272, 438290, 438291, H01L 21336
Patent
active
058997199
ABSTRACT:
A narrow gate FET is formed on a substrate by providing a first layer of polysilicon on the active device regions of the substrate and doping the polysilicon by ion implantation. An etch/polish stop layer of silicon oxide and is deposited on the first layer of polysilicon. Openings are formed in the etch/polish stop layer and the first polysilicon layer to expose the surface of the substrate. An anneal is performed to diffuse N-type impurities from the first layer of polysilicon into the substrate. The heavily doped portions of LDD source/drain regions are formed partially within the substrate and partially within portions of the first layer of polysilicon left on the surface of the substrate. Next, a first implantation of N-type impurities is made across the opening in the first layer of polysilicon. A layer of silicon nitride is deposited over the first layer of polysilicon and within the openings in the first polysilicon layer. Etching is performed to provide nitride spacers on the sidewalls of the openings. A second implantation of P-type impurities is performed to counterdope the channel and to laterally define the lightly doped portions of the source/drain regions. A gate oxide layer is formed on the substrate within the openings. A second layer of polysilicon is deposited on the device, onto the surface of the insulating spacer structures within the openings in the mask, and onto the gate oxide layer at the bottom of the openings. The second polysilicon layer is etched or polished in a process stopping on the etch/polish stop layer to form gate electrodes, with the gate electrodes extending between the spacers in the openings in the first polysilicon layer. The spacers are removed by wet etching and a third implantation of P-type impurities is made to form halo regions around the lightly doped portions of the source/drain regions.
REFERENCES:
patent: 4471522 (1984-09-01), Jambotkar
patent: 5364807 (1994-11-01), Hwang
patent: 5571738 (1996-11-01), Krivokapic
patent: 5688700 (1997-11-01), Kao et al.
patent: 5750430 (1998-05-01), Son
Dang Trung
United Semiconductor Corporation
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