Sub-lithographic gate length transistor using...

Details Sub-lithographic gate length transistor using... Sub-lithographic gate length transistor using...

2008-06-10

2008-06-10

Lebentritt, Michael S. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S287000, C438S244000, C438S330000, C438S268000, C438S270000, C257S330000, C257S331000, C257SE21205, C257SE21438

Reexamination Certificate

active

07384852

ABSTRACT:
A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a specific location using a pre-fabricated hard mask pattern.

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Black, et al., “Integration of Self Assembly for Semiconductor Microelectronics.” IEEE (2005) pp. 87-91.
Black, et al., “Nonometer-Scale Pattern Registration and Alignment by Directed Diblock Copolymer Self-Assembly.” IEEE vol. 3, No. 3, Sep. 2004.
Nealey et al., “Self-Assembling Resists for Nanolithography,” IEEE, 2005, 4 pages.
Singh et al., “Effect of Top Coat and Resist Thickness on Line Edge Roughness,” Proc. of SPIE, 2006, 61530W-1 to 61530W-12, vol. 6153, 12 pages.

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