Coating apparatus – Gas or vapor deposition – With treating means
Reexamination Certificate
1998-05-05
2002-03-26
Mills, Gregory (Department: 1763)
Coating apparatus
Gas or vapor deposition
With treating means
C118S7230MW, C118S697000, C118S695000, C156S345420
Reexamination Certificate
active
06360685
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to fabrication processes suitable for manufacturing semiconductor integrated circuits (“ICs”), and more particularly to a two-step borophosphosilicate glass (“BPSG”) deposition process and related devices and apparatus.
The fabrication sequence of integrated circuits often includes several patterning processes. The patterning processes may define a layer of conductors, such as a patterned metal or polysilicon layer, or may define isolation structures, such as trenches. In many cases the trenches are filled with an insulating, or dielectric, material. This insulating material can serve several functions. The material serves to electrically isolate one region of the IC from another, and can also electrically passivate the surface of the trench. The material also typically provides a base for the next layer of the semiconductor to be built upon.
After patterning a substrate, that material is not flat. The topology of the pattern can interfere with or degrade subsequent wafer processing steps. It is often desirable to create a flat surface over the patterned material. Several methods have been developed to create such a flat, or “planarized”, surface. Examples include depositing a conformnal layer of material of sufficient thickness and polishing the wafer to obtain a flat surface, depositing a conformal layer of material of sufficient thickness and etching the layer back to form a planarized surface, and forming a layer of relatively low-melting point material, such as BPSG, and then heating the wafer sufficiently to cause the BPSG to melt and flow as a liquid, resulting in a flat surface upon cooling. Each process has attributes that make that process desirable for a specific application.
Forming and then melting a layer of BPSG is a desirable layer-forming process for many reasons. The re-flow (melting) temperature of the BPSG is fairly low and the re-flow time is fairly brief, thus re-flow may be accomplished without significantly adding to the thermal budget of the device fabrication sequence. Additionally, BPSG may be doped to various doping concentrations to vary the re-flow characteristics. BPSG can flow to fill very fine features on the surface of a substrate, and can fill trenches of varying widths on a single substrate.
As semiconductor design has advanced, the feature size of the semiconductor devices has dramatically decreased. Many circuits now have features, such as traces or trenches less than a micron across. While the reduction in feature size has allowed higher device density, more chips per wafer, more complex circuits, lower operating power consumption, and lower cost, the smaller geometries have also given rise to new problems, or have resurrected problems that were once solved for larger geometries.
An example of the type of manufacturing challenge presented by sub-micron devices is the ability to completely fill a narrow trench in a void-free manner. To fill a trench with BPSG, a layer of BPSG is first deposited on the patterned substrate. The BPSG layer typically covers the field, as well as walls and bottom of the trench. If the trench is wide and shallow, it is relatively easy to completely fill the trench with BPSG. As the trench gets narrower and the aspect ratio (the ratio of the trench height to the trench width) increases, it becomes more likely that the opening of the trench will “pinch off”.
Pinching off a trench traps a void within the trench. Under certain conditions, the void will be filled during the re-flow process; however, as the trench becomes narrower, it becomes more likely that the void will not be filled during the reflow process. Such voids are undesirable as they can reduce the yield of good chips per wafer and the reliability of the devices. Therefore, it is desirable to be able to fill narrow gaps with BPSG in a void-free manner. It is also desirable that the process used to deposit and reflow BPSG be efficient, reliable, and result in a high yield of devices.
SUMMARY OF THE INVENTION
The present invention provides apparatus and related methods and devices related to doped silicon glass layers. In one embodiment, dopant flow from a liquid precursor is established by diverting the flow directly to a vacuum system, bypassing a deposition chamber. Operation of a valve switches the dopant flow from the vacuum system to the deposition chamber concurrently with the flow of a deposition gas. The deposition gas, such as a silicon-containing gas, may be mixed with the dopant upstream from the valve such that a single valve operates to switch the silicon-containing gas and dopant. Flowing the dopant to the deposition chamber in this fashion forms a layer of doped silicon glass without a dopant-deficient region.
In one application, a two-step deposition process is used to efficiently form a two-layer doped silicon glass film without a dopant-deficient region between the layers using different deposition conditions to form each layer. In another application, a two-step deposition process forms a two-layer doped silicon glass film with different levels of selected dopant or types of dopant in each layer. In another application, a layer of silicon glass without a dopant-deficient region to be used as a dopant source is formed on a semiconductor. One embodiment of the invention is an intermediate IC structure that includes a doped silicon glass layer in contact with a silicon substrate as a source for dopant diffusion, wherein the doped silicon glass layer does not have a dopant-deficient region adjoining the silicon substrate.
REFERENCES:
patent: 5648175 (1997-07-01), Russell et al.
patent: 5935334 (1999-08-01), Fong et al.
patent: 307 995 (1989-03-01), None
patent: 5-291144 (1993-05-01), None
patent: WO 97/24755 (1997-07-01), None
U.S. application No. 08/982,872, Srinivas et al., filed Aug. 1999.
Xia Li-Qun
Yieh Ellie
Applied Materials Inc.
Hassanzadeh P.
Mills Gregory
Townsend and Townsend and Crew
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