Structures and methods for reduction of parasitic...

Details Structures and methods for reduction of parasitic... Structures and methods for reduction of parasitic...

2007-09-28

2010-11-02

Smith, Matthew (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S396000, C438S926000, C438S129000, C438S928000, C257SE21573

Reexamination Certificate

active

07825019

ABSTRACT:
A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

REFERENCES:
patent: 6281049 (2001-08-01), Lee
patent: 2004/0121577 (2004-06-01), Yu et al.
patent: 2005/0088551 (2005-04-01), Lee et al.
patent: 2007/0170547 (2007-07-01), Chang et al.
patent: 2008/0311742 (2008-12-01), Watanabe et al.

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