Structure of metal oxide semiconductor field effect transistor

Details Structure of metal oxide semiconductor field effect transistor Structure of metal oxide semiconductor field effect transistor

2003-07-24

2004-12-28

Thompson, Craig A. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06835611

ABSTRACT:

REFERENCE CITED
1. C. J. Koeneke, et. al., “Schottky MOSFET for VLSI”, in Dig. of IEDM, p.367, 1981 .
2. S. E. Swirhun, et. al., “A VLSI suitable Schottky barrier CMOS process”, IEEE, Trans. Electron Devices, vol.ED-32, No.2, p.194, 1985.
3. B. Y. Tsui, et. al., “A novel process for high-Performance Schottky barrier PMOS”, J. Electrochem. Soc., vol. 136, No.5, p.1456, 1989.
4. C. Wang, et. al., “Sub-50-nm PtSi Schottky source/drain p-MOSFETs”, in Proc. of Device Research Conf., p.72, 1998.
5. C. Wang, et. al., “Sub-40 nm PtSi Schottky source/drain metal-oxide-semiconductor field-effect transistors”, Appl. Phys. Lett., vol.74, No.8, p.1174, 1999.
6. W. Saitoh, et. al., “35 nm metal gate SOI-pMOSFETs with PtSi Schottky source/drain”, in Proc. of Device Research Conf., p.30, 1999.
7. A. Itoh, et. al., Very short channel metal-gate Schottky source/drain SOI-PMOSFETs and their short channel effect”, in Proc. of Device Research Conf., p.77, 2000.
8. H. C. Lin, et. al., “A novel implantless MOS Thin-Film Transistor with simple processing, excellent performance, and ambipolar operation capablity”. in Dig. of IEDM, p.857, 2000.
9. K. Uchida, et. al., “Enhancement of hot-electron generation rate in Schottky source metal-oxide-semiconductor field-effect transistors”, Appl. Phys. Lett., vol.76, No.26, p.3992, 2000.
FIELD OF THE INVENTION
The present invention relates to MOSFET (Metal Oxide Semiconductor Field Effect Transistor) for modifying Schottky Barrier and diminishing Carrier Injection Resistance. More particularly, the present invention employs SOI (Silicon-On-Insulator) device to be a substrate thereof for modifying Schottky Barrier and diminishing Carrier Injection Resistance, and a fabrication process therefor.
BACKGROUND OF THE INVENTION
The MOSFET industry has been working on downscaling for microelectronic devices, particularly for the MOSFET, to increase its features and the density of component. It is very successful in some examples from the early micron till today's deep-submicron for MOSFET, however, it still has some problems for downscaling to nanomicron. Especially, the short channel effect is a very important problem, which is caused by crosswise dopant diffusion; after ion implanting in source and drain electrodes, annealing process may cause the crosswise dopant diffusion.
Lately, the structure of Schottky Barrier has been put in use on nanomicron SOI device. Metal silicide may replace the P-N junction without causing dopant diffusion; therefore, it may solve the problem of short channel effect. The structure of Schottky Barrier has been provided in 10 years ago for improving the latch-up problem, but it also caused high carriers injection resistance in source electrode and high current leakage in drain electrode of Schottky Barrier. Though an asymmetric structure has been provided for solving the problem of current leakage, it could not be accepted by CMOS process due to the different mask process for masking the source region, and the resistance problem still not be solved.
The structure of Schottky Barrier being employed on SOI device may improve the current leakage in drain electrode. Because after forming metal silicide the silicon layer is reacted completely, the area of Schottky Junction is squeezed in the channel for carriers passing through, and the current leakage problem may be improved dramatically. However, the problem of carrier injection resistance is still not solved. Besides, due to the different density channel of N-MOSFET and P-MOSFET respectively, it is necessary to have different metal-silicide for modifying Schottky Barrier, for example, PtSi adapted for P-MOSFET and ErSi
2
for N-MOSFET. Therefore, it may not be available for integrating into the standard MOS process with different materials.
Furthermore, “Sub-gate” has been provided to form “inversion layers” for generating a channel for carriers passing through; however, this kind of process is not accepted for the standard CMOS process, and also, the problem of employing different material is not solved. In addition, it needs high voltage to control the sub-gate, and it also may cause another problem in voltage control.
SUMMARY OF THE INVENTION
Accordingly, the present invention discloses a structure of MOSFET for modifying the Schottky Barrier and diminishing carrier Injection Resistance and method for fabricating the same, which comprises a SOI (Silicon-On-Insulator) device, a MOS (Metal Oxide Semiconductor) formed on said SOI device, and a metal-silicide layer. Said SOI device includes a substrate, an insulation layer formed on said substrate, and a silicon layer formed on said insulation layer. Said MOS is formed on said SOI device. The metal-silicide layer is formed in accordance with a metal self aligned process by a metal layer being deposited on said SOI device and on said MOS for reacting with said silicon layer, and an implant-to-silicide process is employed to form a high-density source region and a high-density drain region for modifying Schottky Barrier and diminishing Carrier Injection Resistance.


REFERENCES:
patent: 6440806 (2002-08-01), Xiang
Streetman, Solid State Electronic Devices, 1990, Prentice-Hall, Inc., Third Edition, pp. 351-352.*
C.J. Koeneke, et al.; “Schottky MOSFET for VLSI”; in Dig. of IEDM, p. 367; 1981.
S.E. Swirhun et al.; “A VLSI Suitable Schottky Barrier CMOS Process”; IEEE, Trans. Electron Devices; vol. ED-32, No. 2; p. 194; 1985.
B.Y. Tsui et al.; “A Novel Process For High-Performance Schottky Barrier PMOS”; J. Electrochem. Soc.; vol. 136, No. 5; p. 1456; 1989.
C. Wang et al.; “Sub-50-nm PtSi Schottky Source/Drain p-MOSFETs”; in Proc. of Device Research Conf.; p/72; 1998.
C. Wang et al.; Sub-50-nm PtSi Schotty Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistors; Appl. Phys. Lett.; vol. 74, No. 8; p. 1174; 1999.
W. Saltoh et al.; “35 nm Metal Gate SOI-p-MOSFETs With PtSi Schottky Source/Drain”; In Proc. of Device Research Conf.; p. 30; 1999.
A. Itoh et al.; “Very Short Channel Metal-Gate Schottky Source/Drain SOI-PMOSFETs And Their Short Channel Effect”; In Proc. of Device Research Conf.; p. 77; 2000.
H.C. Lin et al.; “A Novel Implantless MOS Thin-Film Transistor With Simple Processing, Excellent Performance, and Ambipolar Operation Capability”; in Dig. of IEDM; p. 857; 2000.
K. Uchida et al.; “Enhancement Of Hot-Electron Generation Rate in Schottky Source Metal-Oxide-Semiconductor Field-Effect Transistors”; Appl. Phys. Lett.; vol. 76, No. 26; p. 3992; 2000.

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