Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-07-26
2003-11-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
72, 72, 72, 72, 72
Reexamination Certificate
active
06650009
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of multi chip module having stacked chips. More specifically, the present invention relates to a structure of multi chip module package having stacked chips for semiconductor devices.
2. Description of the Related Art
In the current world full of information, integrated circuits play an important role in daily life. With increasing development in electronics, electronic products are more user friendly and exhibit higher performance. Products are designed such that the features are lighter and more compact. In the semiconductor fabricating process, a semiconductor product having higher integration is possible because of mass production of 0.18 micrometers integrated circuits.
In general, the production of the integrated circuit (IC) includes three stages: silicon wafer production, IC production and IC packaging.
Various technologies for packaging have been developed as competition in the industry has increased. Many fine packages such as chip scale package (CSP), wafer level package or multi chip module (MCM) are manufactured. In the assembly of devices, a multi-level PCB having higher density can be used to allow the IC package to be arranged on the PCB more compactly.
The current package for the integrated circuit has been developed to incorporate a Read Only Memory (ROM), a Static Random Access Memory (SRAM), a flash memory or a Dynamic Random Access Memory (DRAM), a Logic Circuit, and a digital circuit on a chip, so called as System On Chip (SOC) to satisfy the demand for light weight, compact size and perfect performance. An embedded ROM is one of examples of the circuit having both a flash memory and a logic circuit.
However, in the conventional system on chip (SOC), a plurality of chips, such as DRAM, flash memory, Logic Circuit and radio frequency (RF) devices, are incorporated on a chip. Although the functionality and electric property thereof can be thus enhanced, it is more complicate to design a layout in circuit connection. Since the fabricating methods of devices having various functions are different from each other, the integration of devices having various functions becomes complex, resulting in reduced yield and increased cost for fabrication.
Referring to
FIG. 1A
, a conventional structure for multi chip module package is shown.
FIG. 11B
is cross sectional view of
FIG. 1A
taken along
1
B—
1
B.
As shown in
FIGS. 1A and 11B
, a multi chip module (MCM) package is used as an alternative. A main chip
105
, a first chip
106
and a second chip
108
are arranged side-by-side on a substrate
102
. The connection of the main chip
105
, the first chip
106
and the second chip
108
to the substrate
102
is achieved by a glue layer
104
. Wire bonding is subsequently performed to electrically connect the main chip
105
, the first chip
106
, the second chip
108
to the substrate
102
by wires
110
. The main chip
105
, the first chip
106
, the second chip
108
and the wires
110
are encapsulated with a mold compound
114
. Finally, solder balls are mounted thereon to complete a structure for the multi chip module package.
Referring to
FIG. 2A
, a plan view of another conventional structure of multi chip module package is shown.
FIG. 2B
is a cross sectional view of
FIG. 2A
along
2
B—
2
B.
As shown in
FIGS. 2A and 2B
, a main chip
205
, a first chip
206
, a second chip
208
, a third chip
209
and a fourth chip
207
are arranged side-by-side on a substrate
202
. The connection of the main chip
205
, the first chip
206
, the second chip
208
, the third chip
209
and the fourth chip
207
to the substrate is achieved by a glue layer
204
. Wire bonding is subsequently preformed to electrically connect the main chip
205
, the first chip
206
, the second chip
208
, the third chip
209
and the fourth chip
207
to the substrate
202
by wires
210
. The main chip
205
, the first chip
206
, the second chip
208
, the third chip
209
and the fourth chip
207
, the substrate
202
and the wires
210
are encapsulated with a mold compound
214
. Finally, solder balls are mounted thereon to complete a structure of multi chip module package. The conventional structure of multi chip module package is characterized in that devices with multifunctions are integrated into a package. The area occupied by the package devices is large to make routability of the substrate
202
complicate. A substrate
202
having high junction density is, thus, desirably used. The side-by-side arrangement of the main chip
205
, the first chip
206
, the second chip
208
, the third chip
209
and the fourth chip
207
influence the amount of chips accommodated in the multi chip module package. The integration can, thus, be affected to result in increased cost and reduced performance.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a structure of multi chip module package for stacking support chip and having substantially the same size.
It is another object of the present invention to provide a structure for a multi-chip module package that has sufficient routability and stacked chips.
It is still another object of the present invention to provide a structure of multi chip module package that can incorporate more chips and can be used to stack the chips.
According to the above objects of the present invention, comprising at least: a substrate, a main chip, a plurality of chip sets, a plurality of spacers, a plurality of glue layers, a plurality of wires, and a mold compound. The substrate has a front surface and a back surface opposite to the front surface. A plurality of chips are stacked in the form of laminate on the front surface of the substrate to form a plurality of chip sets, which are located next to the main chip. A plurality of spacers are arranged between each two adjacent chips. The connection between the spacers, the main chip, the chips, and the substrate are achieved by a plurality of glue layers. A plurality of wires are used to electrically connect the chips and the main chip to the substrate. Finally, the front surface of the substrate, the main chip, the spacers, the chips, and the glue layers are encapsulated with a mold compound to accomplish the package.
According to a preferred embodiment of the present invention, a structure of multi chip module package having stacked chips is provided to stack memories, such as support chip, and decrease the area occupied by the package devices. The structure of the present invention can also stack chips having substantially the same size to incorporate with more chips to utilize the routability of the substrate more effectively, without the substrate of high junction density. The layout of the side-by-side chips can, thus, be improved to accommodate more stacked chips for the multi chip module package. It leads to enhanced integration which reduces the cost for manufacturers and obtains improved performance.
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Her Tzong-Dar
Huang Chien-Ping
Lo Randy H. Y.
Huynh Andy
Siliconware Precision Industries Co. Ltd.
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