Structure of a DRAM and a manufacturing process thereof

Details Structure of a DRAM and a manufacturing process thereof Structure of a DRAM and a manufacturing process thereof

2001-01-23

2002-07-23

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S254000, C438S396000, C438S397000, C438S640000, C438S656000

Reexamination Certificate

active

06423597

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 89123686, filed Nov. 9, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of integrated circuit (IC) and a manufacturing process for the same. More specifically, the present invention relates a structure of a dynamic random access memory (DRAM) and a manufacturing process for the same.
2. Description of the Related Art
A basic structure of a DRAM cell consists of a metal-oxide-semiconductor (MOS) device and a capacitor. A source/drain region of such a MOS device is electrically connected to a bit line. Another source/drain region of the MOS device not connected to the bit line is electrically connected to the capacitor. The data of the DRAM cell is determined by the charge of the capacitor. In current memory cells, which are small in size, a capacitor is provided on the bit line in order to increase the capacitance of the capacitor. Data dislocation and data refreshment for the capacitor are thereby reduced and operational efficiency is increased. This structure is known as a Capacitor on Bit Line (COB), in which the cross-sectional area of the bottom of the capacitor is increased as much as possible, i.e., the surface area of the capacitor is as large as possible. Furthermore, gates of MOS devices in the same row of memory cells line up to form a word line in a direction orthogonal to the bit line.
Here, conventional production of a DRAM includes three stages summarized as follows:
(1) After the MOS transistors for the memory cell are completed, the substrate is covered with a first insulating layer. A bit line contact in electric contact with the source region is formed in the first insulating layer. A bit line in electric contact with a bit line contact is formed on the first insulating layer.
(2) The substrate is covered with a second insulating layer. A node contact opening is formed in the second and first insulating layers. Such node contact opening penetrates through the second insulating layer between two adjacent bit lines to expose the drain region. Subsequently, the node contact opening is filled with a conductive material to form a node contact.
(3) A conductive layer is formed on the substrate. The conductive layer is patterned by using a photo mask having an irregular pattern to form an irregular bottom electrode. The bottom electrode is in electric contact with the node contact.
However, there are some disadvantages in the conventional production of a capacitor, summarized as follows. First, in stage (2), when the node contact opening is formed in the second and first insulating layers, a self-aligned process cannot be used because of the existing bit line, resulting in a misalignment of the node contact (opening) and the drain region.
Second, in stage (2), the node contact opening exposes the bit line to create a short between the node contact and the bit line formed later.
Third, in stage (3), since the definition of the bottom electrode is not carried out in a self-aligned process, it is not easy to align the bottom electrode with the node contact.
Fourth, in stage (3), since the bottom electrodes having different memory cells have to be separated from each other, the irregular photo mask used for the bottom electrode is required. Therefore, the production of the photomask is complicated and expensive.
These disadvantages result in reduced yield of the product. In addition, another disadvantage is further present in that the resistance of the bit line may be decreased to slow down the operation of thedevices, explained briefly as follows. With decreased linewidth in the current semiconductor process, one way to decrease the resistance of leads so as to increase the operational speed for the devices is to use a low-resistance material. Another is to increase the thickness of the leads so as to increase the cross-sectional area. However, in stage (1) of the conventional process of a DRAM, the resistance of the bit line can be decreased by increasing the thickness of the bit line. This is because the node contact opening is etched from top of the second insulating layer exceeding the bit line until the drain region under the first insulating layer of the bit line is exposed. Therefore, the depth of the node contact opening is very large. In addition, the width of the node contact opening decreases as device integration increases, resulting in a larger aspect ratio for etching. Therefore, etching tends to be incomplete and the electric connection of the node contact (bottom electrode) to the drain electrode is imperfect. Accordingly, the thickness of the bit line in the conventional process of a DRAM cannot be increased sufficiently to prevent the aspect ratio of the node contact opening for etching from being increased. In other words, the cross-sectional area of the bit line cannot be increased, and thus the resistance thereof cannot be decreased.
SUMMARY OF INVENTION
The invention provides a process for fabricating a DRAM, suitable for a substrate on which a plurality of word lines and a plurality of source/drain regions on sides of each of these word lines are formed. In the invention, a plurality of bit line contacts and a plurality of node contacts are formed in electric contact with the source/drain regions. A first patterned insulating layer is formed on the substrate. A plurality of openings is formed in the insulating layer to expose the bit line contacts. The substrate is covered by a first conductive layer and a second insulating layer in sequence. The second insulating layer, the first conductive layer and the first insulating layer are patterned in sequence to form a plurality of bit line stacked structures and a plurality of bit lines electrically connecting to the bit contacts. The node contacts are exposed. The bit line stacked structure forms a plurality of trenches and the bit line stacked structure is orthogonal to the word lines. A plurality of spacers is formed on the sidewalls of the bit line stacked structure. A plurality of second conductive layers is formed conformal to the surfaces of the trenches. Finally, the second conductive layers are patterned to form a plurality of bottom electrodes electrically connected to the node contacts.
The invention also provides a structure for a DRAM, comprising a plurality of word lines, a plurality of source/drain regions, a first insulating layer, a plurality of bit line contact and node contact, a plurality of bit line stacked structure, a plurality of spacers, and a plurality of bottom electrode. In the structure according to the present invention, the word line is located on the substrate. The source/drain region is located at the sides of each of the word lines. The first insulating layer is disposed on the word lines and substrate. The bit line contact and the node contact are located in the first insulating layer and are electrically connected to the source/drain region. The bit line stacked structure is located on the first insulating layer and the bit line contact. These bit line stacked structures are orthogonal to the word lines, and each of the bit line stacked structures is built up by stacking a second insulating layer, a bit line and a third insulating layer from bottom to top, with the bit lines passing through the second insulating layer and electrically connecting to the bit line contacts. The spacers are located on the sidewalls of each of the bit line stacked structures. The trench is formed between each two spacers. The bottom electrode is located on the surface of the trench. Each bottom electrode is electrically connected to one of the node contacts.
As mentioned above, in the process for fabricating DRAM of the present invention, a patterning board for the bottom is formed to expose the node contact while the bit line (stacked structure) is defined. Moreover, a second insulating layer and spacers are provided on the bit line and sides thereof as electric insulation, respectively. As a result, a short circuit

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