Structure of a complementary metal oxide semiconductor sensor

Details Structure of a complementary metal oxide semiconductor sensor Structure of a complementary metal oxide semiconductor sensor

1999-12-29

2003-02-04

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S462000

Reexamination Certificate

active

06515321

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor manufacturing method and a structure. More particularly, the present invention relates to a metal oxide semiconductor sensor that solves that problem of white spot.
2. Description of Related Art
FIG. 1
is a cross-sectional view of a sensor of a conventional complementary metal oxide semiconductor (CMOS) sensor.
In
FIG. 1
, the P-type well
101
is located on an N-type substrate
100
. A first oxide layer
102
and a second oxide layer
103
are located in on the P-type well
101
. The first oxide layer
102
and the second oxide layer
103
define an active region
104
. A gate oxide layer
105
is located on the active region
104
. A gate conductive layer
106
is located on the gate oxide layer
105
. The first spacer
107
and the second spacer
108
are located on the side walls of the gate conductive layer
106
. The first lightly doped drain region
109
and the second lightly doped drain region
110
are located below the first spacer
107
and the second spacer
108
in the P-type substrate
101
. A first source/drain region
112
is located between the first lightly doped drain region
109
and the first field oxide layer
102
in the P-type substrate
101
. A second source/drain region
113
is functioned as a sensor implantation region. Thus constructed, a depletion region is formed along the profile of the second source/drain region, that is, the implantation region
113
, at a junction between the implantation region
113
and the P-well
101
. The induced depletion region is the region between the solid line that outlines the second source/drain region
113
and the dash line illustrated in FIG.
1
.
While operating the conventional CMOS sensor, white spots are often observed on the screen. The white spots occur because of current flowing through the junction between the depletion region and the field oxide layer. The defects caused by the stress applied during forming the field oxide layer, or due to the Koii effect are the main reason that induce the current.
SUMMARY OF THE INVENTION
The present invention provides a fabricating method and a structure of complementary metal oxide semiconductor sensor. In the CMOS sensor, a depletion region is designed away from an field oxide layer. Therefore, the current can not flow along the junction between the depletion region and field oxide layer. And thus, even defects are formed around the field oxide layer, the white spot phenomenon is eliminated.
The invention provides a structure of CMOS sensor. The sensor includes at least a first conductive type well, an isolation on the well, a metal-oxide semiconductor in the well, and a sensor implantation region adjacent to or even overlapping with one side of only one source/drain region of the metal-oxide semiconductor. In addition, the sensor implantation region is distant away from the isolation. That is, between the isolation and the sensor implantation region, there is a portion of well region without being further doped.
With this design, the depletion region induced around the sensor implantation region is not adjacent to the isolation, or is even distant away from the isolation, so that there is no worry that the current may flows to the isolation. Therefore, the white spots can be eliminated from the screen.
The invention provides a fabricating method of CMOS sensor. A substrate having a well, a first and a second isolations on the P-well, and a gate on the P-well between the first and the second isolations is provided. Using a mask to cover a portion of the well between the second isolation and the gate and the second isolation, a first and a second source/drain regions are formed. Therefore, the second source/drain region is formed with a distance away from the second isolation. The first mask is removed. Using a second mask to cover the first and second isolations, the first and second source/drain regions, and a portion of the P-well adjacent to the second isolation, a sensor implantation region is formed. Since the portion of the P-well adjacent to the second isolation is covered by the second mask, the sensor implantation region is not in contact with the second isolation.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5932906 (1999-08-01), Shimizu
patent: 6074904 (2000-06-01), Spikes, Jr. et al.
patent: 6104063 (2000-08-01), Fulford, Jr. et al.
patent: 6165827 (2000-12-01), Ahmad et al.
patent: 6255681 (2001-07-01), Pan
patent: 5-315561 (1993-11-01), None

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