Semiconductor MISFET

Details Semiconductor MISFET Semiconductor MISFET

2001-01-16

2003-02-11

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S410000, C257S412000

Reexamination Certificate

active

06518636

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a MISFET-mounted semiconductor device and a method for fabricating such a semiconductor device.
With the recent advance in LSI toward higher integration, higher-speed operation, lower voltage application, and the like, reduction in sizes of gate electrodes of metal insulator semiconductor field effect transistors (MISFETs) and interconnections is under progress. Currently, in particular, MISFETs with a gate length as small as about 0.1 to 0.15 &mgr;m are just to be put into practical use.
FIGS. 4A through 4E
are cross-sectional views illustrating the steps for fabrication of a conventional semiconductor device including MISFETs of a polysilicon gate structure, which is hereinafter referred to as the first prior art. The fabrication process of the semiconductor device of the first prior art will be described with reference to
FIGS. 4A through 4E
.
In the step shown in
FIG. 4A
, a silicon oxide film, which is to be gate insulating films, is formed on a silicon substrate
101
as a semiconductor substrate. A polysilicon film, which is to be gate electrodes, is formed on the silicon oxide film. On the polysilicon film, a photoresist film
104
having a desired gate electrode pattern is formed by photolithography. Using the photoresist film as a mask, the polysilicon film and the silicon oxide film are patterned by dry etching, to form gate insulating films
102
and gate electrodes
103
. At this stage, the lateral size of the gate electrodes
103
(gate length) is A (for example, 0.15 &mgr;m).
In the step shown in
FIG. 4B
, the photoresist film
104
is removed by ashing with O
2
plasma. During the ashing, exposed side faces of the gate electrodes
103
made of polysilicon in n-channel MISFET formation areas are oxidized by a thickness of about 0.005 &mgr;m, for example, forming plasma oxide films
105
a
having a lateral thickness x
1
(for example, about 0.01 &mgr;m). Although omitted in
FIG. 4B
, a plasma oxide film is also formed on the silicon substrate
101
. In addition, plasma oxide films are also formed on the side faces of gate electrodes in the other areas not shown (p-channel MISFET formation areas, and other transistor formation areas different in the thickness of the gate insulating film).
In the step shown in
FIG. 4C
, impurity ions are implanted in the silicon substrate
101
using the gate electrodes
103
and the plasma oxide films
105
a
as a mask, to form n-type LDD layers
106
for the n-channel MISFETs. This ion implantation is performed using arsenic ions under the conditions of an accelerating energy of 10 keV and a dose of 5.0×10
14
cm
−2
, for example. During this ion implantation, the p-channel MISFET formation areas and the like are covered with a photoresist film. This photoresist film must be removed before formation of lightly-doped source/drain regions for p-channel MISFETs and the like.
FIG. 4D
illustrates the state of the n-channel MISFET just after completion of ashing for removing the photoresist film covering the p-channel MISFET formation areas and the like. Due to this ashing with O
2
plasma, the exposed side faces and top portion of the gate electrode
103
made of polysilicon are further oxidized by a thickness of about 0.005 &mgr;m, to form plasma oxide films
105
having a lateral thickness x
2
(for example, about 0.02 &mgr;m). Although omitted in
FIG. 4D
, a plasma oxide film is also further formed on the silicon substrate
101
.
FIG. 4E
illustrates the state of the MISFET after washing with hydrofluoric acid for removal of particles. The plasma oxide films
105
have been removed with the washing with hydrofluoric acid. The resultant gate electrode
103
has a lateral size (gate length) of B (0.13 &mgr;m assuming that the polysilicon has been oxidized by a thickness of about 0.01 &mgr;m on each side by the twice plasma treatment as described above). That is, the lateral size of the gate electrode is gradually reduced from the original size.
FIGS. 5A through 5E
are cross-sectional views illustrating the steps for fabrication of a conventional semiconductor device including MISFETs of a polymetal gate structure, which is hereinafter referred to as the second prior art. The fabrication process of the semiconductor device of the second prior art will be described with reference to
FIGS. 5A through 5E
.
In the step shown in
FIG. 5A
, a silicon oxide film, which is to be gate insulating films, is formed on a silicon substrate
101
as a semiconductor substrate. On the silicon oxide film, deposited sequentially are a polysilicon film, a tungsten nitride (WN) film or a titanium nitride (TiN) film as a barrier metal film, and a metal film made of tungsten (W), which are to be gate electrodes. A silicon nitride film is then formed on the resultant substrate by LPCVD. On the silicon nitride film, a photoresist film
107
having a desired gate electrode pattern is formed by photolithography. Using the photoresist film
107
as a mask, the silicon nitride film, the metal film, the barrier metal film, the polysilicon film, and the silicon oxide film are patterned, to form gate insulating films
102
, gate electrodes
103
each composed of a bottom gate electrode
103
a
, a barrier metal film
103
b
, and a top gate electrode
103
c
, and gate top insulating films
108
.
In the step shown in
FIG. 5B
, the photoresist film
107
is removed by ashing. Due to the ashing with O
2
plasma, exposed side faces of the gate electrodes
103
in the n-channel MISFET formation areas are oxidized, forming plasma oxide films
110
. Each plasma oxide film
110
is particularly formed thick on the bottom gate electrode
103
a
made of polysilicon having a large oxidation rate, hardly formed on the barrier metal film
103
b
made of WN, and slightly formed on the top gate electrode
103
c
made of W. Although omitted in
FIG. 5B
, a plasma oxide film is also formed on the silicon substrate
101
. Plasma oxide films are also formed on side faces of gate electrodes in the other areas not shown (p-channel MISFET formation areas, and other transistor formation areas different in the thickness of the gate insulating film).
In the step shown in
FIG. 5C
, impurity ions are implanted in the silicon substrate
101
using the gate top insulating films
108
and the gate electrodes
103
as a mask, to form n-type LDD layers
106
for the n-channel MISFETs. During this ion implantation, the p-channel MISFET formation areas and the like are covered with a photoresist film. This photoresist film must be removed before formation of p-type LDD layers for the p-channel MISFETs.
FIG. 5C
illustrates the state after completion of ashing for removing the photoresist film covering the p-channel MISFET formation areas and the like and subsequent washing with hydrofluoric acid for removal of particles. Since the photoresist film covering the p-channel MISFET formation areas and the like is removed by ashing with O
2
plasma as in the removal of the photoresist film
107
shown in
FIG. 5B
, the side faces of the gate electrodes
103
are further oxidized as in the step shown in
FIG. 5B
, increasing the thickness of the plasma oxide films
110
. That is, each plasma oxide film
110
is formed particularly thick on the bottom gate electrode
103
a
made of polysilicon having a large oxidation rate, hardly formed on the barrier metal film
103
b
made of WN, and slightly formed on the top gate electrode
103
c
made of W.
By the washing with hydrofluoric acid for particle removal, the plasma oxide films
110
are removed, resulting in the contour as shown in FIG.
5
C. That is, the side faces of the bottom gate electrodes
103
a
made of polysilicon have been particularly greatly etched, the side faces of the top gate electrodes
103
c
made of W have been slightly etched, and the side faces of the gate top insulating films
108
made of silicon nitride have been hardly etched. As a result, the entire gate electrode has a constricted shape.
In the step shown in
FIG. 5D
, using the gate top insulatin

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