Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1999-12-13
2001-08-14
Graybill, David E. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S798000
Reexamination Certificate
active
06274883
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to an improvement in the structure of a ball grid array substrate and in particular to one having charts for indicating the position of defective chips.
2. Description of the Prior Art
Referring to
FIGS. 1 and 2
, a label
2
must be used for indicating the position of defective chips on the conventional ball grid array substrate
1
at each of the processing stations. However, it is not only ineconomical to mark the relative positions
21
of the defective chips on the label
2
, but also easy for an operator to make mistakes in marking the relative positions of the defective chips, thereby worsening the quality control. In addition, such marking operation must be performed by manual power thus increasing the labor cost.
Therefore, it is an object of the present invention to provide an improved structure of a ball grid array substrate which can obviate and mitigate the above-mentioned drawbacks.
SUMMARY OF THE INVENTION
This invention is related to the structure of a ball grid array substrate with charts for indicating the position of defective chips.
According to a preferred embodiment of the present invention, a ball grid array substrate includes a circumferential edge provided with a plurality of charts each having a plurality of lattices corresponding to positions of chips on the ball grid array substrate for indicating positions of defective chips in different packaging procedures.
It is the primary object of the present invention to provide a ball grid array substrate with charts for indicating the positions of defective chips which can reduce the operation cost.
It is another object of the present invention to provide a ball grid array substrate with charts for indicating positions of defective chips which enables an operator to observe easily whether the chip is good or defective.
It is still another object of the present invention to provide a ball grid array substrate with charts for indicating the position of defective chips which is fit for mass production.
It is still another object of the present invention to provide a ball grid array substrate with charts for indicating the position of defective chips which can reduce the time required for packaging the chips.
It is a further object of the present invention to provide a ball grid array substrate with charts for indicating the position of defective chips which is simple in construction and low in cost.
The foregoing objects and summary provide only a brief introduction to the present invention. To fully appreciate these and other objects of the present invention as well as the invention itself, all of which will become apparent to those skilled in the art, the following detailed description of the invention and the claims should be read in conjunction with the accompanying drawings. Throughout the specification and drawings identical reference numerals refer to identical or similar parts. Many other advantages and features of the present invention will become manifest to those versed in the art upon making reference to the detailed description and the accompanying sheets of drawings in which a preferred structural embodiment incorporating the principles of the present invention is shown by way of illustrative example.
REFERENCES:
patent: 3615463 (1971-10-01), Kuschell
patent: 4426773 (1984-01-01), Hargis
patent: 5153507 (1992-10-01), Fong et al.
patent: 5256578 (1993-10-01), Corely et al.
A & J
Graybill David E.
Orient Semiconductor Electronics Ltd.
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