Structure for preventing salicide bridging and method thereof

Details Structure for preventing salicide bridging and method thereof Structure for preventing salicide bridging and method thereof

2002-07-02

2004-01-13

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S926000, C365S149000

Reexamination Certificate

active

06677199

ABSTRACT:

FIELD OF THE INVENTION
This invention pertains in general to a semiconductor device and, more particularly, to a structure for preventing salicide bridging in a semiconductor device and a method thereof.
BACKGROUND OF THE INVENTION
In modem memory integrated circuits (“ICs”), an important consideration is the speed that stored data may be read or retrieved. Such speed depends partly on the speed of word lines. In the semiconductor industry's continued effort to reduce feature sizes of ICs, the width of word lines is also reduced. Such a reduction leads to an increase in the resistance of the word lines. As is known, higher resistance on a word line reduces its speed, which, in turn, reduces the speed of the memory IC. In order to fabricate high performance ICs, low resistivity on the word line is therefore critical.
In conventional metal-oxide semiconductor (“MOS”) ICs, polysilicon is often used as the gate material. The conductivity of polysilicon is increased by doping, but even when doped at a high concentration, the resistance of doped polysilicon remains high. The resistivity of polysilicon may be further decreased by depositing a layer of metal, such as Ti, over the polysilicon. In the case of a transistor, the metal layer is deposited over the gate structure after the transistor is formed. Only the portion of the metal layer deposited over the polysilicon layer will react with the polysilicon to form silicides. The process for forming suicides is therefore “self-aligned” and is referred to as the salicide process. Through the formation of a suicide layer over a polysilicon gate, the resulting “polycide” has a significantly lower resistivity.
The salicide process has been used in the manufacture of memory ICs. A memory IC generally includes a memory array having a matrix of memory cells, or transistors, together with a plurality of substantially parallel word lines, and a plurality of substantially parallel bit lines. Each of the word lines is substantially perpendicular to each of the bit lines. Each word line generally represents the gates of the transistors in a single row of the memory array, and each bit line generally represents the source or drain regions of the transistors in a single column of the memory array.
FIG. 1
shows a layout of word lines
12
and bit lines
14
in a conventional IC
10
. Because the source and drain regions are diffused regions formed in the IC substrate, bit lines are also known as “buried” bit lines.
An IC that incorporates the memory array component of a memory IC and logic components are known as embedded products. From the manufacturing point of view, the only difference between a logic component and a memory component is that a memory component, i.e., memory cell, requires an additional polysilicon layer. Therefore, to decrease the manufacturing cost of an embedded product, logic components and memory components are formed near simultaneously. During the manufacturing process, the memory components may be masked while certain aspects of the logic components are being manufactured, and vice versa. However, a possible result is that salicides may be unintentionally formed over some active regions that cannot be masked, such as the source and/or drain regions, during a particular step of the manufacturing process. This is known as salicide bridging. Slicide bridging is undesirable because it may render an IC inoperative. Two types of salicide bridging may occur in a memory array.
FIG. 2
shows a cross-sectional view of device
10
shown in
FIG. 1
along the periphery, or A-A′ direction, of the device array (not numbered). Referring to
FIG. 2
, a layer of salicide
18
is formed over a substrate
16
of device
10
and electrically connects two of the non-consecutive or non-adjacent bit lines
14
-
1
and
14
-
2
. Bit lines
14
-
1
and
14
-
2
extend through the array more than the other bit lines. As indicated in
FIG. 2
, an electrical short is created between two bit lines
14
-
1
and
14
-
2
, which are n-type diffused regions.
A second type of salicide bridging is shown in FIG.
3
.
FIG. 3
is a cross-sectional view of device
10
shown in
FIG. 1
along the center portion, or B-B′ direction, of the device array. Referring to
FIG. 3
, salicide
18
is formed over substrate
16
, connecting a number of bit lines
14
. As indicated in
FIG. 3
, electrical shorts are created between and among bit lines
14
.
SUMMARY OF THE INVENTION
In accordance with the invention, there is provided a semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plurality of the bit lines, a first dummy word line disposed at a periphery of the memory array, wherein the first dummy word line is substantially parallel to the plurality of word lines and overlaps at least two non-adjacent bit lines.
Also in accordance with the present invention, there is provided a semiconductor device that includes a memory array comprising a plurality of transistors, and a plurality of non-memory transistors, wherein the memory array includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, each of the plurality of the word lines being substantially perpendicular to each of the plurality of the bit lines, and a first dummy word line disposed at a periphery of the memory array, wherein the first dummy word line is substantially parallel to the plurality of word lines and overlaps at least one of the plurality of bit lines.
In accordance with the present invention, there is also provided a method for manufacturing a semiconductor device that includes forming a plurality of substantially parallel bit lines, forming a plurality of substantially parallel word lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plurality of the bit lines, depositing a layer of tetraethyl orthosilicate over the plurality of bit lines and plurality of word lines, wherein the amount of tetraethyl orthosilicate deposited on top of the plurality of word line having a thickness greater than half the distance separate adjacent word lines, and etching back the tetraethyl orthosilicate layer.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 4748596 (1988-05-01), Ogura et al.
patent: 5001669 (1991-03-01), Cho et al.
patent: 5448516 (1995-09-01), Tsukikawa et al.

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