Structure for packaging semiconductor chip

Details Structure for packaging semiconductor chip Structure for packaging semiconductor chip

1998-03-31

2000-10-10

Whitehead, Jr., Carl

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

257778, 257786, H01L 2348

Patent

active

061304808

ABSTRACT:
Described herein are a structure and a method for packaging a semiconductor chip. The structure comprises a semiconductor chip having a plurality of bumps formed thereon, a substrate having copper-made wiring patterns with the bumps joined thereto, which are formed so as to correspond to forming positions of the bumps, and a polyimide tape having adhesive layers provided on both surfaces for joining the semiconductor chip and the substrate to one another upon positioning. A spacing defined between the semiconductor chip and the substrate is sealed with a resin layer. A material for the substrate is selected so that a thermal expansion coefficient of the substrate is substantially equal to that of the polyimide tape. Owing to the above construction, it is possible to reduce the chance that a contact failure may occur, by increasing bonding powers between the bumps and the wiring patterns and avoid cracks from being produced on the surface of the semiconductor chip due to a change in temperature at its manufacture.

REFERENCES:
patent: 5379191 (1995-01-01), Carey et al.
patent: 5444301 (1995-08-01), Song et al.
Tetsuya Koyama et al., "Advanced CSP and Substrate Technologies," Proceedings. 1996 International Symposium on Microelectronics (SPIE vol. 2920), 1996 International Symposium on Microelectronics, Minneapolis, MN, USA Oct. 8-10, 1996, pp. 265-270.

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