Structure for improving interlevel conductor connections

Details Structure for improving interlevel conductor connections Structure for improving interlevel conductor connections

2003-05-19

2004-06-22

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C257S774000

Reexamination Certificate

active

06753607

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an interconnection structure and process used in semiconductor manufacturing and, more particularly, to a structure and method for improving the reliability of connections between different layers of metal or conducting material in the fabrication of integrated circuits.
2. Description of Prior Art
In order to improve the device speed of logic on sub-quarter micron semiconductor circuits, copper has gained popularity as an interconnect material. This takes advantage of copper's low electrical resistivity and superior resistance to electromigration. As the device dimensions shrink, the resistance-capacitance (RC) time delay of the interconnect system becomes one of the most important limitation factors to the performance of the integrated circuit. In order to minimize the signal propagation delay, it is inevitable to use low dielectric constant materials, such as inter-layer and intra-layer dielectrics (ILDs). While many low-k materials have been used as ILDs, silicon nitride with a high dielectric constant is a likely candidate for the etch-stop layer required in copper damascene structures. Therefore, it would be desirable to replace silicon nitride by new materials with lower dielectric constants, in order to further reduce the effective dielectric constants to further reduce the effective dielectric constant of the Cu interconnect system. A continuing interest relates to low stress and thermally stable low-k amorphous silicon carbide-based films deposited by plasma-enhanced chemical vapor deposition using organosilicon gases.
At present, a glue layer is used to prevent Cu from oxidation during deposition of the etch stop layer. A prototypical structure, in ascending order, includes: Cu/glue layer/etch stop layer. In certain instances, the glue layer may hinder throughput, as well as result in process instability due to thickness variations. In accordance with the present invention, a structure and method for improving the reliability of connections between different layers of metal or conducting material in the fabrication of integrated circuits is disclosed.
SUMMARY OF THE INVENTION
The present invention relates to an improved integrated circuit structure including adjacent conductive and dielectric layers having a continuous, planar top surface, produced by a process which comprises treating the surface with a silane compound, followed by depositing an etch stop layer over the surface, wherein a glue layer is not applied to the surface.


REFERENCES:
patent: 6287990 (2001-09-01), Cheung et al.
patent: 6316351 (2001-11-01), Chen et al.
patent: 6465341 (2002-10-01), Pramanick
patent: 6465345 (2002-10-01), Nogami et al.
patent: 6498112 (2002-12-01), Martin et al.

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