Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-06-07
2011-06-07
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
Reexamination Certificate
active
07958477
ABSTRACT:
A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is provided. The failure analysis tool includes a computer infrastructure operable to determine a risk area for wiring layer failure during solder bump formation by determining a distance from a center of a chip to a location for a solder bump processing and identifying an area at an edge of the location for the solder bump processes at a predetermined distance and greater from the center of the chip.
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Daubenspeck Timothy H.
Gambino Jeffrey P.
Muzzy Christopher D.
Sauter Wolfgang
Zimmerman Jeffrey S.
Canale Anthony
International Business Machines - Corporation
Roberts Mlotkowski Safran & Cole P.C.
Whitmore Stacy A
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