Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-04-26
2011-04-26
Potter, Roy K (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S565000
Reexamination Certificate
active
07932566
ABSTRACT:
An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell.
REFERENCES:
patent: 5534724 (1996-07-01), Nagamine
patent: 6381166 (2002-04-01), Yoshida et al.
patent: 2007/0168898 (2007-07-01), Gupta et al.
Webb, C., “45 nm Design for Manufacturing,” Intel Technology Journal, Intel's 45nm CMOS Technology, vol. 12, Issue 2, Jun. 17, 2008, pp. 121-130.
Guo Ta-Pen
Hou Yung-Chin
Li Ping Chung
Lu Lee-Chung
Tien Li-Chun
Potter Roy K
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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