Structure and method of manufacturing a semiconductor memory dev

Details Structure and method of manufacturing a semiconductor memory dev Structure and method of manufacturing a semiconductor memory dev

1993-10-07

1995-03-07

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257408, H01L 2914, H01L 2978

Patent

active

053960980

ABSTRACT:
In a semiconductor memory device, and in particular in a NAND-type ROM memory cell, the transistors of a memory cell region and a peripheral circuit portion are manufactured to include a first and second impurity regions. The second impurity region has a higher impurity density impurity than the first impurity region. A third impurity region is added which has a higher impurity density and shallower depth than the impurity density of the first impurity region. Accordingly, the conventional transistor structure of the peripheral circuit portion is maintained while the transistors of the memory cell are optimized to have ideal electrical characteristics, including an increased current driving capability.

REFERENCES:
patent: 4672419 (1987-06-01), McDavid
patent: 4728617 (1988-03-01), Woo et al.
patent: 4746624 (1988-05-01), Cham et al.

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