Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-09-23
2004-07-27
Wilson, Allan R. (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S300000, C257S305000, C257S309000, C257S310000, C257S311000, C257S499000, C257S581000, C257S506000, C257S776000, C438S218000, C438S219000, C438S250000, C438S253000, C438S255000, C438S244000, C438S427000
Reexamination Certificate
active
06767781
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a process of forming a bitline contact and, more particularly, to a method of forming bitline contacts for a vertical dram array using a bitline contact mask and a structure thereof.
2. Background Description
Random Access Memory (RAM) is a type of volatile memory which is typically used for temporary storage of program data in a computer system. There are several types of RAM, including Static RAM (SRAM) and Dynamic RAM (DRAM). In SRAM, data does not need to be periodically rewritten, and is maintained as long as power is provided to the memory chip. On the other hand, DRAM must be continually rewritten in order for it to maintain the data. DRAM is small and inexpensive and is thus used for most system memory.
A DRAM memory array includes a table of cells which are comprised of capacitors. These capacitors contain one or more “bits” of data, depending upon the chip configuration. The table of cells is addressed via row and column decoders which receive signals from clock generators. In order to minimize the package size, the row and column addresses are multiplexed into row and column address buffers. Access transistors called “sense amps” are connected to each column and provide the read and restore operations of the DRAM memory array. Since the cells are capacitors that discharge for each read operation, the sense amp must restore the data before the end of the access cycle. It is known that separate address, data and control lines limit the access speed of the device.
Formation of the control lines of the DRAM array is of critical importance to the operational speed and robustness of the DRAM array. In current processing techniques, borderless bitline contacts are formed by means of a contact/hole mask. Current DRAM cell sizes are of the order of 8F
2
. For cell sizes below 8F
2
, it has been proposed to vertically twist the bitlines between two bitline levels. In general, this technique causes a loss in area in the DRAM array. This, in turn, limits the density of the columns and rows of bitlines, as well as causing different potentials of the bitlines. Performance and robustness of the DRAM device may thus be compromised using these techniques.
SUMMARY OF THE INVENTION
The present invention is directed to a process of forming a bitline contact and, more particularly, to a method of forming line bitline contacts for a vertical DRAM array using a bitline contact mask. The method of the present invention allows vertical bitline twisting without loss of area in the DRAM array.
In one aspect of the present invention, gate conductor lines with a capping layer are formed on a substrate. An oxide layer is deposited on the capping layer and between the gate conductor lines. A line bitline mask is formed over portions of the oxide layer. The mask is a line mask which is easier to print than a contact/hole mask. The mask is used to etch the oxide layer to the capping layer of the gate conductor lines, and to etch the oxide layer between the gate conductor lines down to the substrate. A silicon layer is deposited on the substrate and between gate conductor lines and non etched portions of the oxide layer. This silicon layer is removed from the top planar or non-etched portions of the oxide by means of a planarizing technique such as Chemical Mechanical Polishing (CMP). A bitline (M
0
) TEOS layer is deposited on the silicon layer and non etched portions of the oxide layer, and a masking and etching operation of portions of the bitline (M
0
) TEOS layer are performed. M
0
metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M
0
) layer to form left and right bitlines.
In another aspect of the present invention, a bitline contact for a vertical DRAM array is provided. The bitline contacts include gate conductor lines formed on a substrate. A polysilicon layer is formed between the gate conductor lines, and an oxide layer is formed over at least one of the gate conductor lines. Metal is formed over the gate conductor lines on opposing sides of the oxide layer thereby forming a left bitline and a right bitline. The left and right bitlines are vertically non-twisted.
REFERENCES:
patent: 5700706 (1997-12-01), Juengling
patent: 5747844 (1998-05-01), Aoki et al.
patent: 5789289 (1998-08-01), Jeng
patent: 5864181 (1999-01-01), Keeth
patent: 6091100 (2000-07-01), Wu
patent: 6310399 (2001-10-01), Feurle et al.
patent: 6686668 (2004-02-01), Nesbit et al.
Bergner Wolfgang
Divakaruni Ramachandra
Faltermeier Jonathan E.
Nesbit Larry A.
Abate Joseph P.
International Business Machines - Corporation
Ortiz Edgardo
Whitham Curtis & Christofferson, P.C.
Wilson Allan R.
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