Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-11-18
2010-02-09
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21431, C257SE21415
Reexamination Certificate
active
07659172
ABSTRACT:
A method for forming a field effect transistor (FET) device includes forming a gate conductor and gate dielectric on an active device area of a semiconductor wafer, the semiconductor wafer including a buried insulator layer formed over a bulk substrate and a semiconductor-on-insulator layer initially formed over the buried insulator layer. Source and drain extensions are formed in the semiconductor-on-insulator layer, adjacent opposing sides of the gate conductor, and source and drain sidewall spacers are formed adjacent the gate conductor. Remaining portions of the semiconductor-on-insulator layer adjacent the sidewall spacers and are removed so as to expose portions of the buried insulator layer. The exposed portions of the buried insulator layer are removed so as to expose portions of the bulk substrate. A semiconductor layer is epitaxially grown on the exposed portions of the bulk substrate and the source and drain extensions, and source and drain implants are formed in the epitaxially grown layer.
REFERENCES:
patent: 6407427 (2002-06-01), Oh
patent: 6521949 (2003-02-01), Assaderaghi et al.
patent: 7091071 (2006-08-01), Thean et al.
patent: 2002/0171107 (2002-11-01), Cheng et al.
patent: 2004/0248369 (2004-12-01), Wang et al.
patent: 2005/0121731 (2005-06-01), Maszara
patent: 2005/0148147 (2005-07-01), Keating et al.
patent: 2005/0151193 (2005-07-01), Wong
patent: 2006/0115949 (2006-06-01), Zhang et al.
patent: 2006/0228842 (2006-10-01), Zhang et al.
patent: 5206455 (1993-08-01), None
Nayfeh Hasan M.
Waite Andrew
Advanced Micro Devices, Inc. (AMD)
Cantor & Colburn LLP
Coleman W. David
International Business Machines - Corporation
Scarlett Shaka
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